公开(公告)号：US20200135549A1

公开(公告)日：2020-04-30

申请号：US16283341

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Harsono Simka ,  Mark Stephen Rodder

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/522

Abstract: In a method of making a semiconductor device, the method includes: forming a first conductive layer over a substrate; forming an insulating layer on the first conductive layer; forming a via through the insulating layer to expose the first conductive layer; forming a self-assembled monolayer (SAM) over a bottom of the via; forming a barrier layer at a sidewall of the via; removing the SAM over the bottom of the via; and forming a second conductive layer over the barrier layer and the bottom of the via such that the first conductive layer is electrically connected to the second conductive layer without the barrier layer between the first conductive layer and the second conductive layer at the bottom of the via.

公开(公告)号：US20240347537A1

公开(公告)日：2024-10-17

申请号：US18363637

申请日：2023-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mehdi Saremi ,  Aravindh Kumar ,  Ming He ,  Muhammed Ahosan Ul Karim ,  Rebecca Park ,  Harsono Simka

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/823807 ,  H01L29/0865 ,  H01L29/0882

Abstract: A method for manufacturing a semiconductor device according to one or more embodiments may include growing a first epitaxy layer at a first side and a second side of a stack of gates and channels, applying a sacrificial layer on the first epitaxy layer, growing a second epitaxy layer on the sacrificial layer, removing the sacrificial layer, and depositing a metal layer on the first epitaxy layer and the second epitaxy layer at the first side of the stack of gates and channels.

公开(公告)号：US20230175133A1

公开(公告)日：2023-06-08

申请号：US18062502

申请日：2022-12-06

Applicant: The Regents of the University of California ,  Merck Patent GmbH ,  Samsung Electronics Co., Ltd.

Inventor： Andrew Kummel ,  Michael Breeden ,  Victor Wang ,  Ravindra Kanjolia ,  Mansour Moinpour ,  Harsono Simka

IPC: C23C16/455 ,  H01L21/285 ,  H01L23/532 ,  H01L23/522 ,  C23C16/18 ,  C23C16/56

CPC classification number: C23C16/45553 ,  C23C16/18 ,  C23C16/56 ,  H01L21/28568 ,  H01L23/5226 ,  H01L23/53209

Abstract: Described are low resistivity metal layers/films, such as low resistivity ruthenium (Ru) layers/films, and methods of forming low resistivity metal films. Ru layers/films with close-to-bulk resistivity can be prepared on substrates using Ru(CpEt)2 + O2 ALD, as well as a two-step ALD process using Ru(DMBD)(CO)3 + TBA (tertiary butyl amine) to nucleate the substrate and Ru(EtCp)2 + O2 to increase layer/film thickness. The Ru layer/films and methods of preparing Ru layers/films described herein may be suitable for use in barrierless via-fills, as well as at M0/M1 interconnect layers.

公开(公告)号：US10957579B2

公开(公告)日：2021-03-23

申请号：US16530075

申请日：2019-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yung Bae Kim ,  Harsono Simka ,  Jong Hyun Lee

IPC: H01L21/768

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a first conductive layer on a substrate and selectively forming a second insulating layer on the first insulating layer. The first insulating layer may include a recess, and the first conductive layer may be in the recess of the first insulating layer. The second insulating layer may include a first opening exposing a surface of the first conductive layer. The methods may also include forming a third insulating layer on the second insulating layer and the first conductive layer, forming a second opening extending through the third insulating layer and exposing the first conductive layer, and forming a second conductive layer in the second opening.

公开(公告)号：US10825723B2

公开(公告)日：2020-11-03

申请号：US16283341

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Harsono Simka ,  Mark Stephen Rodder

IPC: H01L23/49 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528

Abstract: In a method of making a semiconductor device, the method includes: forming a first conductive layer over a substrate; forming an insulating layer on the first conductive layer; forming a via through the insulating layer to expose the first conductive layer; forming a self-assembled monolayer (SAM) over a bottom of the via; forming a barrier layer at a sidewall of the via; removing the SAM over the bottom of the via; and forming a second conductive layer over the barrier layer and the bottom of the via such that the first conductive layer is electrically connected to the second conductive layer without the barrier layer between the first conductive layer and the second conductive layer at the bottom of the via.

公开(公告)号：US20240405128A1

公开(公告)日：2024-12-05

申请号：US18420348

申请日：2024-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aravindh Kumar ,  Mehdi Saremi ,  Ming He ,  Muhammed Ahosan Ul Karim ,  Rebecca Park ,  Harsono Simka

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A field-effect transistor includes a substrate, a channel on the substrate including a stem including silicon extending in a vertical direction from the substrate and a number of prongs including silicon extending in a horizontal direction from the stem and spaced apart from each other along the vertical direction, an interfacial layer surrounding the stem and the prongs of the channel, a dielectric layer on the interfacial layer and surrounding the stem and the prongs of the channel, and a metal gate on the dielectric layer and surrounding the stem and the prongs of the channel.

公开(公告)号：US11705363B2

公开(公告)日：2023-07-18

申请号：US17326973

申请日：2021-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ming He ,  Harsono Simka ,  Rebecca Park

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76813 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226

Abstract: A method and electronic device are provided. The method includes patterning a metal in a first dielectric layer, depositing a first metal layer over the patterned metal, forming a nanowall under the first metal layer such that the nanowall is in contact with the patterned metal in the first dielectric layer, depositing a second dielectric layer on the first dielectric layer, removing at least a portion of the nanowall, thereby forming a channel in the second dielectric layer, and depositing a metal via in the channel such that the metal via is in contact with the patterned metal in the first dielectric layer.

公开(公告)号：US20230086084A1

公开(公告)日：2023-03-23

申请号：US17554483

申请日：2021-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Inchan Hwang ,  Gunho Jo ,  Jeonghyuk Yim ,  Byounghak Hong ,  Kang-ill Seo ,  Ming He ,  JaeHyun Park ,  Mehdi Saremi ,  Rebecca Park ,  Harsono Simka ,  Daewon Ha

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234

Abstract: Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

公开(公告)号：US20240413232A1

公开(公告)日：2024-12-12

申请号：US18356776

申请日：2023-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mehdi Saremi ,  Aravindh Kumar ,  Rebecca Park ,  Muhammed Ahosan Ul Karim ,  Ming He ,  Harsono Simka

IPC: H01L29/775 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: According to one or more embodiments of the present disclosure, a semiconductor device is described. The semiconductor device may include a substrate, a channel portion on the substrate between a source region and a drain region, and a gate on the channel. The channel portion may include a first portion extending in a first direction and at least one second portion protruding from the first portion in a second direction crossing the first portion.

公开(公告)号：US11978668B2

公开(公告)日：2024-05-07

申请号：US17546470

申请日：2021-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ming He ,  Harsono Simka ,  Anthony Dongick Lee ,  Seowoo Nam ,  Sang Hoon Ahn

IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/76895 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76819 ,  H01L21/76829 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/535

Abstract: Integrated circuit devices including a via and methods of forming the same are provided. The methods may include forming a conductive wire structure on a substrate. The conductive wire structure may include a first insulating layer and a conductive wire stack in the first insulating layer, and the conductive wire stack may include a conductive wire and a mask layer stacked on the substrate. The method may also include forming a recess in the first insulating layer by removing the mask layer, the recess exposing the conductive wire, forming an etch stop layer and then a second insulating layer on the first insulating layer and in the recess of the first insulating layer, and forming a conductive via extending through the second insulating layer and the etch stop layer and contacting the conductive wire.