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公开(公告)号：US20180152190A1
公开(公告)日：2018-05-31
申请号：US15426330
申请日：2017-02-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung-seok SONG , Byoung-joo Yoo , Chang-kyung Seong
CPC classification number: H03L7/0818 , H03K5/131 , H03L7/07 , H03L7/0807 , H03L7/0814 , H04L7/0025 , H04L7/0037 , H04L7/0087 , H04L7/0331
Abstract: A phase interpolator includes a control circuit configured to generate a selection control signal that corresponds to a selected coarse phase interval, and generate a weight setting signal for generating a phase interpolation clock signal with an interpolated phase within the coarse phase interval; a phase selector configured to receive a plurality of inversion delay clock signal pairs, select at least two inversion delay clock signal pairs from the plurality of inversion delay clock signal pairs based on the selection control signal, select and output a selection delay clock signal pair corresponding to the coarse phase interval from the selected at least two inversion delay clock signal pairs; and a phase mixer configured to receive the selection delay clock signal pair from the phase selector and generate the phase interpolation clock signal based on the weight setting signal.
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公开(公告)号：US10171091B2
公开(公告)日：2019-01-01
申请号：US15426330
申请日：2017-02-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung-seok Song , Byoung-joo Yoo , Chang-kyung Seong
Abstract: A phase interpolator includes a control circuit configured to generate a selection control signal that corresponds to a selected coarse phase interval, and generate a weight setting signal for generating a phase interpolation clock signal with an interpolated phase within the coarse phase interval; a phase selector configured to receive a plurality of inversion delay clock signal pairs, select at least two inversion delay clock signal pairs from the plurality of inversion delay clock signal pairs based on the selection control signal, select and output a selection delay clock signal pair corresponding to the coarse phase interval from the selected at least two inversion delay clock signal pairs; and a phase mixer configured to receive the selection delay clock signal pair from the phase selector and generate the phase interpolation clock signal based on the weight setting signal.
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