公开(公告)号：US20240407152A1

公开(公告)日：2024-12-05

申请号：US18642174

申请日：2024-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eulji JEONG ,  Sukhoon KIM ,  Hyojung NOH ,  Sungnam LYU ,  Byounghoon LEE

IPC: H10B12/00

Abstract: A gate structure comprising: a first conductive pattern; a first seed pattern on a lower surface and a first portion of a sidewall of the first conductive pattern, wherein the first seed pattern includes a first material, and the first conductive pattern includes a second material that is different from the first material; and a gate insulation pattern that is in contact with a second portion of the sidewall of the first conductive pattern and the first seed pattern, wherein the first material has a first work function, and the second material has a second work function, and wherein the first work function is lower than the second work function.

公开(公告)号：US20250132198A1

公开(公告)日：2025-04-24

申请号：US18669981

申请日：2024-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunho KANG ,  Minsik KIM ,  Yeonuk KIM ,  Seran OH ,  Byounghoon LEE ,  Jangeun LEE

IPC: H01L21/768 ,  H01L21/3105

Abstract: A method of manufacturing a semiconductor device, the method includes forming interconnection lines buried in a first interlayer insulating layer, the interconnection lines having exposed upper surfaces, selectively forming a preliminary low dielectric constant layer including a polymer containing silicon (Si) or an oligomer containing silicon (Si) on an upper surface of the first interlayer insulating layer, forming a low dielectric constant layer by performing ultraviolet (UV) and ozone (O3) treatments on the preliminary low dielectric constant layer, forming an etch stop layer on the low dielectric constant layer, forming a second interlayer insulating layer on the etch stop layer, and forming a via connected to at least one of the interconnection lines by removing a portion of the second interlayer insulating layer and depositing a conductive material. The via has a shape bent along an upper surface and a side surface of the low dielectric constant layer.

公开(公告)号：US20240258393A1

公开(公告)日：2024-08-01

申请号：US18544767

申请日：2023-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojung NOH ,  Sungnam LYU ,  Byounghoon LEE ,  Jangeun LEE ,  Eulji JEONG

IPC: H01L29/423 ,  H10B12/00

CPC classification number: H01L29/42372 ,  H01L29/42364 ,  H10B12/315 ,  H01L29/4236

Abstract: A gate structure includes a first conductive pattern including a first metal or a first metal compound and being doped with a second metal or silicon; a second conductive pattern on the first conductive pattern, the second conductive pattern including a third metal; and a gate insulation pattern covering a lower surface and a sidewall of the first conductive pattern and a sidewall of the second conductive pattern; wherein a work function of the second metal is smaller than a work function of the first metal and is smaller than a work function of the first metal compound.

公开(公告)号：US20220231018A1

公开(公告)日：2022-07-21

申请号：US17712272

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon LEE ,  Jongho PARK ,  Wandon KIM ,  Sangjin HYUN

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10 ,  H01L29/06

Abstract: A semiconductor device includes a plurality of semiconductor patterns that are sequentially stacked and spaced apart from each other on a substrate, and a gate electrode on the plurality of semiconductor patterns. The gate electrode includes a capping pattern and a work function pattern that are sequentially stacked on the plurality of semiconductor patterns. The capping pattern includes a first metal nitride layer including a first metal element, and a second metal nitride layer including a second metal element whose work function is greater than a work function of the first metal element. The first metal nitride layer is disposed between the second metal nitride layer and the plurality of semiconductor patterns. The first metal nitride layer is thinner than the second metal nitride layer.