公开(公告)号：US20240421070A1

公开(公告)日：2024-12-19

申请号：US18409491

申请日：2024-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunjung LEE ,  Sanghoon AHN ,  Donggon YOO ,  Jangeun LEE ,  Jeongwon HWANG

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a substrate including an active pattern; a channel pattern on the active pattern; a source/drain pattern electrically connected to the channel pattern; a gate electrode on the channel pattern; an interlayer dielectric layer on the gate electrode, wherein the interlayer dielectric layer includes a recess; a via in the recess; a wiring line on the interlayer dielectric layer and electrically connected to the via; and an adhesion layer between the wiring line and an upper surface of the interlayer dielectric layer, wherein an upper surface of the via is closer than the upper surface of the interlayer dielectric layer to the substrate in a first direction, wherein the first direction is perpendicular to an upper surface of the substrate and wherein a portion of the adhesion layer is on a portion of an inner sidewall of the recess.

公开(公告)号：US20230178439A1

公开(公告)日：2023-06-08

申请号：US17950512

申请日：2022-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangeun LEE ,  Hyojung NOH ,  Minwoo SONG ,  Yongho HA ,  Jeongwon HWANG

IPC: H01L21/8234 ,  H01L27/108 ,  H01L29/06

CPC classification number: H01L21/823493 ,  H01L21/823462 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/0623

Abstract: A method of manufacturing a semiconductor device is provided. The method of manufacturing a semiconductor device includes an forming a trench in a substrate, forming a gate dielectric layer on the trench, forming a gate layer on the gate dielectric layer, and annealing the gate dielectric layer and the gate layer, wherein, after the first annealing operation, the gate layer includes a molybdenum-tantalum alloy.

公开(公告)号：US20240258393A1

公开(公告)日：2024-08-01

申请号：US18544767

申请日：2023-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojung NOH ,  Sungnam LYU ,  Byounghoon LEE ,  Jangeun LEE ,  Eulji JEONG

IPC: H01L29/423 ,  H10B12/00

CPC classification number: H01L29/42372 ,  H01L29/42364 ,  H10B12/315 ,  H01L29/4236

Abstract: A gate structure includes a first conductive pattern including a first metal or a first metal compound and being doped with a second metal or silicon; a second conductive pattern on the first conductive pattern, the second conductive pattern including a third metal; and a gate insulation pattern covering a lower surface and a sidewall of the first conductive pattern and a sidewall of the second conductive pattern; wherein a work function of the second metal is smaller than a work function of the first metal and is smaller than a work function of the first metal compound.

公开(公告)号：US20230146530A1

公开(公告)日：2023-05-11

申请号：US18052726

申请日：2022-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangeun LEE ,  Minjoo LEE ,  Eunyoung LEE ,  Minsik KIM

IPC: H01L27/06 ,  H01L21/02 ,  H10B12/00

CPC classification number: H01L27/0605 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10888

Abstract: An integrated circuit device according may include a plurality of gate structures embedded in a substrate, a direct contact on the substrate between the plurality of gate structures, and a bit line electrode layer on the direct contact. The bit line electrode layer has a thickness of about 10 nm to 30 nm. The bit line electrode layer may include a molybdenum tungsten (MoW) alloy including molybdenum (Mo) a range of about 25 at % to about 75 at %.

公开(公告)号：US20220262738A1

公开(公告)日：2022-08-18

申请号：US17475506

申请日：2021-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jangeun LEE ,  Minjoo LEE ,  Wandon KIM ,  Hyunbae LEE

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: An integrated circuit chip includes a base layer. A first wiring layer is disposed on the base layer and includes a plurality of first wiring structures. A second wiring layer is disposed on the first wiring layer and includes a plurality of second wiring structures. Each of the plurality of second wiring structures has a first metal layer and a second metal layer respectively having different resistivities. A third wiring layer is disposed on the second wiring layer and includes a plurality of third wiring structures. Each of the plurality of first wiring structures comprises Ru, Mo, W, or an alloy thereof. Each of the plurality of second wiring structures comprises Ru, Mo, W, or an alloy thereof. Each of the plurality of third wiring structures comprises a material different from a material of the plurality of first wiring structures.

公开(公告)号：US20250132198A1

公开(公告)日：2025-04-24

申请号：US18669981

申请日：2024-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunho KANG ,  Minsik KIM ,  Yeonuk KIM ,  Seran OH ,  Byounghoon LEE ,  Jangeun LEE

IPC: H01L21/768 ,  H01L21/3105

Abstract: A method of manufacturing a semiconductor device, the method includes forming interconnection lines buried in a first interlayer insulating layer, the interconnection lines having exposed upper surfaces, selectively forming a preliminary low dielectric constant layer including a polymer containing silicon (Si) or an oligomer containing silicon (Si) on an upper surface of the first interlayer insulating layer, forming a low dielectric constant layer by performing ultraviolet (UV) and ozone (O3) treatments on the preliminary low dielectric constant layer, forming an etch stop layer on the low dielectric constant layer, forming a second interlayer insulating layer on the etch stop layer, and forming a via connected to at least one of the interconnection lines by removing a portion of the second interlayer insulating layer and depositing a conductive material. The via has a shape bent along an upper surface and a side surface of the low dielectric constant layer.