公开(公告)号：US20240250000A1

公开(公告)日：2024-07-25

申请号：US18468317

申请日：2023-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghyuk YIM ,  Wandon KIM ,  Hyunbae LEE ,  Hyoseok CHOI ,  Sunghwan KIM ,  Junki PARK

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate including an active pattern, a source/drain pattern on the active pattern, an active contact on the source/drain pattern; a lower power line in the substrate, a lower contact that vertically connects the active contact to the lower power line, a conductive layer between the lower contact and the lower power line, and a power delivery network layer on a bottom surface of the substrate. The conductive layer may include silicon (Si) and a first element. The first element may include a transition metal or a metalloid. A concentration of the first element may decrease in a direction from the lower contact toward the lower power line.

公开(公告)号：US20220262738A1

公开(公告)日：2022-08-18

申请号：US17475506

申请日：2021-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jangeun LEE ,  Minjoo LEE ,  Wandon KIM ,  Hyunbae LEE

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: An integrated circuit chip includes a base layer. A first wiring layer is disposed on the base layer and includes a plurality of first wiring structures. A second wiring layer is disposed on the first wiring layer and includes a plurality of second wiring structures. Each of the plurality of second wiring structures has a first metal layer and a second metal layer respectively having different resistivities. A third wiring layer is disposed on the second wiring layer and includes a plurality of third wiring structures. Each of the plurality of first wiring structures comprises Ru, Mo, W, or an alloy thereof. Each of the plurality of second wiring structures comprises Ru, Mo, W, or an alloy thereof. Each of the plurality of third wiring structures comprises a material different from a material of the plurality of first wiring structures.

公开(公告)号：US20220231018A1

公开(公告)日：2022-07-21

申请号：US17712272

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon LEE ,  Jongho PARK ,  Wandon KIM ,  Sangjin HYUN

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10 ,  H01L29/06

Abstract: A semiconductor device includes a plurality of semiconductor patterns that are sequentially stacked and spaced apart from each other on a substrate, and a gate electrode on the plurality of semiconductor patterns. The gate electrode includes a capping pattern and a work function pattern that are sequentially stacked on the plurality of semiconductor patterns. The capping pattern includes a first metal nitride layer including a first metal element, and a second metal nitride layer including a second metal element whose work function is greater than a work function of the first metal element. The first metal nitride layer is disposed between the second metal nitride layer and the plurality of semiconductor patterns. The first metal nitride layer is thinner than the second metal nitride layer.

公开(公告)号：US20220139910A1

公开(公告)日：2022-05-05

申请号：US17578982

申请日：2022-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwoo KIM ,  Yoon Tae HWANG ,  Wandon KIM ,  Hyunbae LEE

IPC: H01L27/088 ,  H01L29/49 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern and extending in a first direction; a source/drain pattern on the active pattern and adjacent to a side of the gate electrode; and an active contact in a contact hole on the source/drain pattern, wherein the active contact includes a first contact in a lower region of the contact hole, the first contact including a barrier pattern and a conductive pattern; a diffusion barrier layer on the first contact; and a second contact on the diffusion barrier layer, and a top surface of the diffusion barrier layer is coplanar with a top surface of the barrier pattern of the first contact.

公开(公告)号：US20160372382A1

公开(公告)日：2016-12-22

申请号：US15158885

申请日：2016-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： HUYONG LEE ,  Wandon KIM ,  Jaeyeol SONG ,  Sangjin HYUN

IPC: H01L21/8238 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/7848

Abstract: A semiconductor device includes a gate structure crossing an active pattern of a substrate. The semiconductor device may include a gate dielectric pattern between the substrate and the gate electrode. The gate structure includes a gate electrode, a capping pattern on the gate electrode, and one or more low-k dielectric layers at least partially covering one or more sidewalls of the capping pattern. The gate structure may include spacers at opposite sidewalk of the gate electrode and separate low-k dielectric layers between the capping pattern and the spacers. The capping pattern may have a width that is smaller than a width of the gate electrode. The capping pattern has a first dielectric constant, and the one or more low-k dielectric layers have a second dielectric constant. The second dielectric constant is smaller than the first dielectric constant. The second dielectric constant may he greater than or equal to 1.

Abstract translation: 半导体器件包括与衬底的有源图案交叉的栅极结构。 半导体器件可以包括在衬底和栅电极之间的栅极电介质图案。 栅极结构包括栅电极，栅电极上的覆盖图案以及至少部分覆盖封盖图案的一个或多个侧壁的一个或多个低k电介质层。 栅极结构可以包括在栅电极的相对的人行道处的隔离物和封盖图案和间隔物之间​​的分离的低k电介质层。 封盖图案的宽度可以小于栅电极的宽度。 封盖图案具有第一介电常数，并且一个或多个低k电介质层具有第二介电常数。 第二介电常数小于第一介电常数。 第二介电常数可以大于或等于1。

公开(公告)号：US20250107179A1

公开(公告)日：2025-03-27

申请号：US18663867

申请日：2024-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonkeun CHUNG ,  Geunwoo KIM ,  Wandon KIM ,  Hyoseok CHOI

IPC: H01L29/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is an integrated circuit device and a method of manufacturing same, the integrated circuit device including: a fin-type active region on a substrate, a pair of insulating spacers on the fin-type active region and the substrate and defining a first space, a gate dielectric film contacting the gate line in the first space, a gate contact plug having a conductive bottom surface contacting a top contact portion of the gate line in the first space, and a capping insulating pattern including an insulating bottom surface, a pair of first insulating sidewalls, and a second insulating sidewall, the insulating bottom surface contacting a local top surface of the gate line in the first space, the pair of first insulating sidewalls contacting the pair of insulating spacers, and the second insulating sidewall contacting the gate contact plug, wherein an insulating top surface of the capping insulating pattern and a conductive top surface of the gate contact plug extend along one plane.

公开(公告)号：US20240128319A1

公开(公告)日：2024-04-18

申请号：US18322234

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunwoo KIM ,  Wandon KIM ,  Jaeseoung PARK ,  Hyunbae LEE ,  Jeonghyuk YIM

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/518 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes a first conductive pattern on a substrate, a second conductive pattern surrounding at least a portion of the first conductive pattern and covering a lower portion of a sidewall of the first conductive pattern, an upper insulating structure on the first conductive pattern and the second conductive pattern, and an upper conductive pattern extending in a vertical direction through the upper insulating structure. The upper conductive pattern includes a main plug portion overlapping the first conductive pattern and the second conductive pattern in the vertical direction, and a vertical extension portion extending from a local region of the main plug portion toward the substrate, the vertical extension portion covering an upper portion of the sidewall of the first conductive pattern and overlapping the second conductive pattern in the vertical direction.

公开(公告)号：US20230197806A1

公开(公告)日：2023-06-22

申请号：US18113116

申请日：2023-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namgyu CHO ,  Minwoo SONG ,  Ohseong KWON ,  Wandon KIM ,  Hyeokjun SON ,  Jinkyu JANG

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L29/7855 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854 ,  H01L29/66439 ,  H01L29/4966

Abstract: A semiconductor device includes: an active fin disposed on a substrate; a gate structure overlapping the active fin; source/drain regions disposed on both sides of the gate structure and on the active fin; and contact structures respectively connected to the source/drain regions, wherein the gate structure includes: a pair of gate spacers spaced apart from each other to provide a trench; a first gate electrode disposed in the trench and extending along an upper surface and a lateral surface of the active fin; a second gate electrode disposed on the first gate electrode in the trench, wherein the first gate electrode is not disposed between the second gate electrode and the pair of gate spacers; and a gate insulating film disposed between the pair of gate spacers and interposed between the first gate electrode and the active fin.

公开(公告)号：US20220392899A1

公开(公告)日：2022-12-08

申请号：US17886878

申请日：2022-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Tae HWANG ,  Sunjung LEE ,  Heonbok LEE ,  Geunwoo KIM ,  Wandon KIM

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

公开(公告)号：US20220367336A1

公开(公告)日：2022-11-17

申请号：US17515954

申请日：2021-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euibok LEE ,  Wandon KIM

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/311

Abstract: An integrated circuit (IC) device includes a first conductive line in a closed curve defining a local area on a substrate. The first conductive line has a first end portion and a second end portion. A second conductive line is outside the local area. The second conductive line has a linear line portion along the closed curve and a bulging end portion along the closed curve. The bulging end portion protrudes from the linear line portion toward the first end portion of the first conductive line in the second lateral direction and protrudes further than the first end portion to the outside of the local area. A method of manufacturing an IC device includes forming a first reference pattern having a mandrel hole. A reference spacer is formed inside the mandrel hole. A second reference pattern is formed. The second reference pattern has a shift hole.