公开(公告)号：US20240381643A1

公开(公告)日：2024-11-14

申请号：US18616343

申请日：2024-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo Kim ,  Juyeon Jung ,  Byoungtaek Kim ,  Gwangwe Yoo

IPC: H10B43/27 ,  H01L23/00 ,  H10B41/27

Abstract: A semiconductor device includes a gate electrode structure including gate electrodes spaced apart in a first direction perpendicular to an upper surface of a substrate, each gate electrode extending in a second direction parallel to the upper surface of the substrate, a memory channel structure, and a support pattern array including support patterns spaced apart in the second direction and a third direction crossing the second direction, wherein each support pattern has a shape including three vertices and three sides, and wherein a first vertex of a first support pattern closest to a second support pattern and a first vertex of the second support pattern closest to the first support pattern are not aligned in the third direction but have different positions in the second direction.

公开(公告)号：US20220384479A1

公开(公告)日：2022-12-01

申请号：US17689391

申请日：2022-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjoo Song ,  Byoungtaek Kim ,  Haemin Lee

IPC: H01L27/11582 ,  H01L23/00 ,  H01L27/11565

Abstract: A semiconductor device includes a peripheral circuit structure, a semiconductor layer, a source conductive layer, a connecting mold layer, a support conductive layer, a buried insulating layer, a gate stack structure, a mold structure, a channel structure and a supporter through the gate stack structure, a THV through the mold structure and the buried insulating layer, a dam structure between the gate stack structure and the mold structure, an upper supporter layer on the dam structure, and a word line separation layer through the gate stack structure and the upper supporter layer. The dam structure includes a first spacer, a second spacer inside the first spacer, a lower supporter layer connected to the upper supporter layer and partially on or covering an inner side wall of the second spacer, and an air gap with a side wall defined by the second spacer and a top end defined by the lower supporter layer.