公开(公告)号：US11800712B2

公开(公告)日：2023-10-24

申请号：US17339129

申请日：2021-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyeon Jung ,  Kwanyong Kim ,  Haemin Lee ,  Juyoung Lim ,  Wonseok Cho

IPC: H01L27/11582 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes a substrate having a first region, a second region, and a third region main separation regions extending in the first direction and apart from each other in a second direction, first auxiliary separation regions extending in the first direction and spaced apart from each other in the second direction, and second auxiliary separation regions extending in the first direction and spaced apart from each other in the second direction. The first auxiliary separation regions are at a first pitch in the second direction between the main separation regions, the second auxiliary separation regions are disposed at a second pitch, smaller than the first pitch in the second direction between the main separation regions, and the first auxiliary separation regions and the second auxiliary separation regions are shifted from each other in the second direction.

公开(公告)号：US20220208789A1

公开(公告)日：2022-06-30

申请号：US17528233

申请日：2021-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haemin Lee ,  Jongsoo Kim ,  Hyeonjoo Song ,  Juyeon Jung

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11519 ,  H01L23/528

Abstract: A semiconductor device comprises a stack structure including interlayer insulating layers and gate layers alternately stacked on a lower structure; and a memory vertical structure, separation structures, and support vertical structures penetrating the stack structure, wherein the gate layers include a lower gate layer, an upper gate layer, and intermediate gate layers, wherein the separation structures include a first separation structure, wherein the support vertical structures include a first inner support vertical structure penetrating the lower gate layer, the intermediate gate layers, and the upper gate layer, and adjacent to the first separation structure, wherein a portion of the first inner support vertical structure is directly connected to the first separation structure on the same level as the upper gate layer, and wherein a portion of the first inner support vertical structure is spaced apart from the first separation structure on the same level as the lower gate layer.

公开(公告)号：US20250056803A1

公开(公告)日：2025-02-13

申请号：US18931231

申请日：2024-10-30

Applicant: Samsung Electronics Co., Ltd

Inventor： Haemin Lee ,  Jongsoo Kim ,  Hyeonjoo Song ,  Juyeon Jung

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device comprises a stack structure including interlayer insulating layers and gate layers alternately stacked on a lower structure; and a memory vertical structure, separation structures, and support vertical structures penetrating the stack structure, wherein the gate layers include a lower gate layer, an upper gate layer, and intermediate gate layers, wherein the separation structures include a first separation structure, wherein the support vertical structures include a first inner support vertical structure penetrating the lower gate layer, the intermediate gate layers, and the upper gate layer, and adjacent to the first separation structure, wherein a portion of the first inner support vertical structure is directly connected to the first separation structure on the same level as the upper gate layer, and wherein a portion of the first inner support vertical structure is spaced apart from the first separation structure on the same level as the lower gate layer.

公开(公告)号：US12160991B2

公开(公告)日：2024-12-03

申请号：US17528233

申请日：2021-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haemin Lee ,  Jongsoo Kim ,  Hyeonjoo Song ,  Juyeon Jung

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device comprises a stack structure including interlayer insulating layers and gate layers alternately stacked on a lower structure; and a memory vertical structure, separation structures, and support vertical structures penetrating the stack structure, wherein the gate layers include a lower gate layer, an upper gate layer, and intermediate gate layers, wherein the separation structures include a first separation structure, wherein the support vertical structures include a first inner support vertical structure penetrating the lower gate layer, the intermediate gate layers, and the upper gate layer, and adjacent to the first separation structure, wherein a portion of the first inner support vertical structure is directly connected to the first separation structure on the same level as the upper gate layer, and wherein a portion of the first inner support vertical structure is spaced apart from the first separation structure on the same level as the lower gate layer.

公开(公告)号：US20240381643A1

公开(公告)日：2024-11-14

申请号：US18616343

申请日：2024-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo Kim ,  Juyeon Jung ,  Byoungtaek Kim ,  Gwangwe Yoo

IPC: H10B43/27 ,  H01L23/00 ,  H10B41/27

Abstract: A semiconductor device includes a gate electrode structure including gate electrodes spaced apart in a first direction perpendicular to an upper surface of a substrate, each gate electrode extending in a second direction parallel to the upper surface of the substrate, a memory channel structure, and a support pattern array including support patterns spaced apart in the second direction and a third direction crossing the second direction, wherein each support pattern has a shape including three vertices and three sides, and wherein a first vertex of a first support pattern closest to a second support pattern and a first vertex of the second support pattern closest to the first support pattern are not aligned in the third direction but have different positions in the second direction.