公开(公告)号：US20220208789A1

公开(公告)日：2022-06-30

申请号：US17528233

申请日：2021-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haemin Lee ,  Jongsoo Kim ,  Hyeonjoo Song ,  Juyeon Jung

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11519 ,  H01L23/528

Abstract: A semiconductor device comprises a stack structure including interlayer insulating layers and gate layers alternately stacked on a lower structure; and a memory vertical structure, separation structures, and support vertical structures penetrating the stack structure, wherein the gate layers include a lower gate layer, an upper gate layer, and intermediate gate layers, wherein the separation structures include a first separation structure, wherein the support vertical structures include a first inner support vertical structure penetrating the lower gate layer, the intermediate gate layers, and the upper gate layer, and adjacent to the first separation structure, wherein a portion of the first inner support vertical structure is directly connected to the first separation structure on the same level as the upper gate layer, and wherein a portion of the first inner support vertical structure is spaced apart from the first separation structure on the same level as the lower gate layer.

公开(公告)号：US20220384479A1

公开(公告)日：2022-12-01

申请号：US17689391

申请日：2022-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjoo Song ,  Byoungtaek Kim ,  Haemin Lee

IPC: H01L27/11582 ,  H01L23/00 ,  H01L27/11565

Abstract: A semiconductor device includes a peripheral circuit structure, a semiconductor layer, a source conductive layer, a connecting mold layer, a support conductive layer, a buried insulating layer, a gate stack structure, a mold structure, a channel structure and a supporter through the gate stack structure, a THV through the mold structure and the buried insulating layer, a dam structure between the gate stack structure and the mold structure, an upper supporter layer on the dam structure, and a word line separation layer through the gate stack structure and the upper supporter layer. The dam structure includes a first spacer, a second spacer inside the first spacer, a lower supporter layer connected to the upper supporter layer and partially on or covering an inner side wall of the second spacer, and an air gap with a side wall defined by the second spacer and a top end defined by the lower supporter layer.

公开(公告)号：US20220093639A1

公开(公告)日：2022-03-24

申请号：US17465928

申请日：2021-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjoo Song ,  Haemin Lee

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/48

Abstract: Integrated circuit devices may include: a gate stack extending on a substrate in a first direction that may be parallel to a main surface of the substrate, the gate stack including a plurality of gate electrodes overlapping each other in a vertical direction that may be perpendicular to the main surface of the substrate; a channel structure extending through the gate stack and extending in the vertical direction; a word line cut opening extending through the gate stack in the vertical direction and extending in the first direction; and an upper support layer on the gate stack and including a hole overlapping the word line cut opening in the vertical direction. An upper surface of the channel structure is in contact with a lower surface of the upper support layer.

公开(公告)号：US12075622B2

公开(公告)日：2024-08-27

申请号：US17465928

申请日：2021-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjoo Song ,  Haemin Lee

IPC: H10B43/27 ,  H01L23/48 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/481 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: Integrated circuit devices may include: a gate stack extending on a substrate in a first direction that may be parallel to a main surface of the substrate, the gate stack including a plurality of gate electrodes overlapping each other in a vertical direction that may be perpendicular to the main surface of the substrate; a channel structure extending through the gate stack and extending in the vertical direction; a word line cut opening extending through the gate stack in the vertical direction and extending in the first direction; and an upper support layer on the gate stack and including a hole overlapping the word line cut opening in the vertical direction. An upper surface of the channel structure is in contact with a lower surface of the upper support layer.

公开(公告)号：US12058859B2

公开(公告)日：2024-08-06

申请号：US17174497

申请日：2021-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangmin Kim ,  Joongshik Shin ,  Hongik Son ,  Hyeonjoo Song

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A vertical memory device includes a gate electrode structure formed on a substrate including a cell array region and a pad region, a channel, contact plugs, and support structures. The gate electrode structure includes gate electrodes extending in a second direction and stacked in a staircase shape in a first direction on the pad region. The channel extends through the gate electrode structure on the cell array region. The contact plugs contact corresponding ones of steps, respectively, of the gate electrode structure. The support structures extend through the corresponding ones of the steps, respectively, and extend in the first direction on the pad region. The support structure includes a filling pattern and an etch stop pattern covering a sidewall and a bottom surface thereof. An upper surface of each of the support structures is higher than that of the channel.

公开(公告)号：US20210399009A1

公开(公告)日：2021-12-23

申请号：US17174497

申请日：2021-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangmin Kim ,  Joongshik Shin ,  Hongik Son ,  Hyeonjoo Song

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: A vertical memory device includes a gate electrode structure formed on a substrate including a cell array region and a pad region, a channel, contact plugs, and support structures. The gate electrode structure includes gate electrodes extending in a second direction and stacked in a staircase shape in a first direction on the pad region. The channel extends through the gate electrode structure on the cell array region. The contact plugs contact corresponding ones of steps, respectively, of the gate electrode structure. The support structures extend through the corresponding ones of the steps, respectively, and extend in the first direction on the pad region. The support structure includes a filling pattern and an etch stop pattern covering a sidewall and a bottom surface thereof. An upper surface of each of the support structures is higher than that of the channel.

公开(公告)号：US20250056803A1

公开(公告)日：2025-02-13

申请号：US18931231

申请日：2024-10-30

Applicant: Samsung Electronics Co., Ltd

Inventor： Haemin Lee ,  Jongsoo Kim ,  Hyeonjoo Song ,  Juyeon Jung

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device comprises a stack structure including interlayer insulating layers and gate layers alternately stacked on a lower structure; and a memory vertical structure, separation structures, and support vertical structures penetrating the stack structure, wherein the gate layers include a lower gate layer, an upper gate layer, and intermediate gate layers, wherein the separation structures include a first separation structure, wherein the support vertical structures include a first inner support vertical structure penetrating the lower gate layer, the intermediate gate layers, and the upper gate layer, and adjacent to the first separation structure, wherein a portion of the first inner support vertical structure is directly connected to the first separation structure on the same level as the upper gate layer, and wherein a portion of the first inner support vertical structure is spaced apart from the first separation structure on the same level as the lower gate layer.

公开(公告)号：US12176389B2

公开(公告)日：2024-12-24

申请号：US17468814

申请日：2021-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyemi Lee ,  Seongjae Go ,  Hyeonjoo Song ,  Sunjoong Park ,  Hanyong Park

IPC: H01L29/06 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  G11C5/06

Abstract: A semiconductor device including a peripheral circuit layer on a substrate; a lower stack and upper stack on the substrate; a stopper layer on the upper stack and including an insulating material; an upper mold layer on the stopper layer; a cell channel structure extending through the layers, a side surface of the cell channel structure contacting the stopper layer; first and second capping layers; a word line separation structure including a protrusion protruding toward the stopper layer; and a bit line contact plug connected to the cell channel structure, wherein an inner side surface of the stopper layer is offset from an inner side surface of the upper stack, and in contact with the word line separation structure.

公开(公告)号：US12160991B2

公开(公告)日：2024-12-03

申请号：US17528233

申请日：2021-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haemin Lee ,  Jongsoo Kim ,  Hyeonjoo Song ,  Juyeon Jung

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device comprises a stack structure including interlayer insulating layers and gate layers alternately stacked on a lower structure; and a memory vertical structure, separation structures, and support vertical structures penetrating the stack structure, wherein the gate layers include a lower gate layer, an upper gate layer, and intermediate gate layers, wherein the separation structures include a first separation structure, wherein the support vertical structures include a first inner support vertical structure penetrating the lower gate layer, the intermediate gate layers, and the upper gate layer, and adjacent to the first separation structure, wherein a portion of the first inner support vertical structure is directly connected to the first separation structure on the same level as the upper gate layer, and wherein a portion of the first inner support vertical structure is spaced apart from the first separation structure on the same level as the lower gate layer.