公开(公告)号：US10943918B2

公开(公告)日：2021-03-09

申请号：US16516756

申请日：2019-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Sung-Gil Kim ,  Jung-Hwan Kim ,  Chan-Hyoung Kim ,  Woo-Sung Lee

IPC: H01L27/00 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.

公开(公告)号：US11626414B2

公开(公告)日：2023-04-11

申请号：US16903026

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil Kim ,  Sungjin Kim ,  Seulye Kim ,  Jung-Hwan Kim ,  Chan-Hyoung Kim

IPC: H01L27/11568 ,  H01L27/11556 ,  G11C5/06 ,  H01L27/11582 ,  G11C5/02

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. A semiconductor memory device includes a stack structure that includes a plurality of electrodes and a plurality of dielectric layers that are alternately stacked on a substrate, a vertical channel structure that penetrates the stack structure, and a conductive pad on the vertical channel structure. The vertical channel structure includes a semiconductor pattern and a vertical dielectric layer between the semiconductor pattern and the electrodes. An upper portion of the semiconductor pattern includes an impurity region that includes a halogen element. The upper portion of the semiconductor pattern is adjacent to the conductive pad.

公开(公告)号：US20210098480A1

公开(公告)日：2021-04-01

申请号：US16903026

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil Kim ,  Sungjin Kim ,  Seulye Kim ,  Jung-Hwan Kim ,  Chan-Hyoung Kim

IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  G11C5/06

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. A semiconductor memory device includes a stack structure that includes a plurality of electrodes and a plurality of dielectric layers that are alternately stacked on a substrate, a vertical channel structure that penetrates the stack structure, and a conductive pad on the vertical channel structure. The vertical channel structure includes a semiconductor pattern and a vertical dielectric layer between the semiconductor pattern and the electrodes. An upper portion of the semiconductor pattern includes an impurity region that includes a halogen element. The upper portion of the semiconductor pattern is adjacent to the conductive pad.

公开(公告)号：US11521987B2

公开(公告)日：2022-12-06

申请号：US17195756

申请日：2021-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Sung-Gil Kim ,  Jung-Hwan Kim ,  Chan-Hyoung Kim ,  Woo-Sung Lee

IPC: H01L27/00 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524

Abstract: A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.

公开(公告)号：US20200176467A1

公开(公告)日：2020-06-04

申请号：US16516756

申请日：2019-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Sung-Gil Kim ,  Jung-Hwan Kim ,  Chan-Hyoung Kim ,  Woo-Sung Lee

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.