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    Vertical memory devices and method of manufacturing the same
    6.
    发明授权
    Vertical memory devices and method of manufacturing the same 有权
    垂直存储器件及其制造方法

    公开(公告)号：US09276133B2

    公开(公告)日：2016-03-01

    申请号：US14184262

    申请日：2014-02-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Hwan Kim ,  Jun-Kyu Yang ,  Hun-Hyeong Lim ,  Jae-ho Choi ,  Ki-Hyun Hwang

    IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28

    CPC classification number: H01L29/7926 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/66833

    Abstract: A method of manufacturing a vertical memory device is disclosed. In the method, a plurality of insulation layers and a plurality of first sacrificial layers are alternately stacked on a substrate. A plurality of holes is formed through the plurality of insulation layers and first sacrificial layers. A plasma treatment process is performed to oxidize the first sacrificial layers exposed by the holes. A plurality of second sacrificial layer patterns project from sidewalls of the holes. A blocking layer pattern, a charge storage layer pattern and a tunnel insulation layer pattern are formed on the sidewall of the holes that cover the second sacrificial layer patterns. A plurality of channels is formed to fill the holes. The first sacrificial layers and the second sacrificial layer patterns are removed to form a plurality of gaps exposing a sidewall of the blocking layer pattern. A plurality of gate electrodes is formed to fill the gaps.

    Abstract translation: 公开了制造垂直存储器件的方法。 在该方法中，多个绝缘层和多个第一牺牲层交替堆叠在基板上。 通过多个绝缘层和第一牺牲层形成多个孔。 进行等离子体处理工艺以氧化由孔暴露的第一牺牲层。 多个第二牺牲层图案从孔的侧壁突出。 在覆盖第二牺牲层图案的孔的侧壁上形成阻挡层图案，电荷存储层图案和隧道绝缘层图案。 形成多个通道以填充孔。 去除第一牺牲层和第二牺牲层图案以形成暴露阻挡层图案的侧壁的多个间隙。 形成多个栅电极以填充间隙。

    Semiconductor device and method of manufacturing the same
    8.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08962444B2

    公开(公告)日：2015-02-24

    申请号：US14053913

    申请日：2013-10-15

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Jung-Hwan Kim ,  Sunggil Kim ,  HongSuk Kim ,  Guk-Hyon Yon ,  Hunhyeong Lim

    IPC: H01L21/76 ,  H01L21/762

    CPC classification number: H01L21/76224 ,  H01L21/28273 ,  H01L21/32155 ,  H01L21/764 ,  H01L27/11524

    Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon pattern in a gas including second p-type dopants, forming a dielectric layer and a conductive layer on the thermally treated poly-silicon pattern and the device isolation pattern, etching the conductive layer, the dielectric layer, and the thermally treated poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate respectively.

    Abstract translation: 提供制造半导体器件的方法。 该方法包括在衬底上形成掺杂有第一p型掺杂剂的多晶硅层，蚀刻多晶硅层和衬底以形成多晶硅图案和沟槽，从而形成覆盖层的下侧壁的器件隔离图案 沟槽中的多晶硅图案，在包括第二p型掺杂剂的气体中热处理多晶硅图案，在热处理的多晶硅图案和器件隔离图案上形成电介质层和导电层，蚀刻导电 层，电介质层和热处理的多晶硅图案，以分别形成控制栅极，电介质图案和浮置栅极。

    Semiconductor package
    9.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11817424B2

    公开(公告)日：2023-11-14

    申请号：US17212332

    申请日：2021-03-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Hwan Kim

    IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00

    CPC classification number: H01L25/0657 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/14

    Abstract: A semiconductor package includes a lower semiconductor chip having a first surface and a second surface, an upper semiconductor chip on the first surface, a first insulating layer between the first surface and the upper semiconductor chip, a second insulating layer between the first insulating layer and the upper semiconductor chip, and a connection structure penetrating the first insulating layer and the second insulating layer and being connected to the lower semiconductor chip and the upper semiconductor chip. The connection structure includes a first connecting portion and a second connecting portion, which are respectively disposed in the first insulating layer and the second insulating layer. A width of the second connecting portion is greater than a width of the first connecting portion. A thickness of the second connecting portion is greater than a thickness of the first connecting portion.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    10.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20210305276A1

    公开(公告)日：2021-09-30

    申请号：US17076306

    申请日：2020-10-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunggil Kim ,  Seulye Kim ,  Jung-Hwan Kim

    IPC: H01L27/11582 ,  H01L27/11556

    Abstract: A semiconductor memory device includes a substrate with a cell array region and a connection region, an electrode structure including electrodes stacked on the substrate and having a staircase structure on the connection region, a vertical channel structure on the cell array region to penetrate the electrode structure and electrically connected to the substrate, a dummy structure on the connection region to penetrate the staircase structure, and a first sidewall oxide pattern interposed between the substrate and the dummy structure. The dummy structure includes an upper portion that is on the substrate, a middle portion that is in contact with the first sidewall oxide pattern, and a lower portion that is below the middle portion. With increasing vertical distance from the upper portion, a diameter of the middle portion decreases until it reaches its smallest value and then increases.

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