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公开(公告)号:US09905664B2
公开(公告)日:2018-02-27
申请号:US15604646
申请日:2017-05-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyun Namkoong , Dong-Kyum Kim , Jung-Hwan Kim , Jung Geun Jee , Han-Vit Yang , Ji-Man Yoo
IPC: H01L29/792 , H01L21/336 , H01L29/423 , H01L21/28 , H01L29/66 , H01L29/788 , H01L27/11519 , H01L27/11521 , H01L27/11565 , H01L27/11582
CPC classification number: H01L29/42328 , H01L21/28273 , H01L21/28282 , H01L27/11519 , H01L27/11521 , H01L27/11565 , H01L27/11582 , H01L29/42324 , H01L29/42344 , H01L29/66825 , H01L29/7881 , H01L29/7926
Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.
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公开(公告)号:US09659743B2
公开(公告)日:2017-05-23
申请号:US14963654
申请日:2015-12-09
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung-Hwan Kim , Min-Kook Kim , Yu-Sin Yang , Sang-Kil Lee , Chung-Sam Jun
IPC: H01J37/22 , H01J37/21 , H01J37/285 , H01J37/31
CPC classification number: H01J37/222 , H01J37/28 , H01J37/285 , H01J37/31 , H01J2237/226 , H01J2237/2445 , H01J2237/2527 , H01J2237/2561
Abstract: A spatial image having 2D spatial information is obtained from a surface of a sample by an image creating method. The surface of the sample is milled to obtain an elemental image having material information from the milled surface. The spatial image and the elemental image are composed to form a 2D spatial/elemental image.
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公开(公告)号:US09595612B2
公开(公告)日:2017-03-14
申请号:US15006522
申请日:2016-01-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung-Hwan Kim , Hun-Hyeoung Leam , Tae-Hyun Kim , Seok-Woo Nam , Hyun Namkoong , Yong-Seok Kim , Tea-Kwang Yu
IPC: H01L29/76 , H01L29/78 , H01L21/28 , H01L21/762 , H01L21/8234 , H01L27/115 , H01L29/423 , H01L29/66 , H01L29/06 , H01L29/10
CPC classification number: H01L29/785 , H01L21/28282 , H01L21/308 , H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/1079 , H01L29/42352 , H01L29/66818 , H01L29/66833 , H01L29/7851 , H01L29/7854 , H01L2029/7858
Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
Abstract translation: 半导体器件包括限定形成在半导体衬底中的有源区的隔离层。 在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。 执行第一舍入处理以围绕活动区域的边缘部分。 在隔离层上进行第二凹陷处理。 执行第二舍入处理以围绕活动区域的边缘部分。
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公开(公告)号:US09412636B2
公开(公告)日:2016-08-09
申请号:US14682231
申请日:2015-04-09
Applicant: Samsung Electronics Co., Ltd
Inventor: Chungsun Lee , Jung-Seok Ahn , Kwang-chul Choi , Un-Byoung Kang , Jung-Hwan Kim , Joonsik Sohn , Jeon Il Lee
IPC: H01L21/58 , H01L21/683 , H01L21/304 , B32B37/12 , B32B37/18 , B32B37/24 , B32B37/26 , B32B38/04 , B32B38/10 , B32B38/16 , H01L21/02 , H01L21/768 , H01L23/00
CPC classification number: H01L21/6835 , B32B37/1284 , B32B37/18 , B32B37/24 , B32B37/26 , B32B38/04 , B32B38/10 , B32B38/162 , B32B2037/268 , B32B2315/08 , B32B2457/14 , H01L21/02057 , H01L21/02126 , H01L21/304 , H01L21/6836 , H01L21/76898 , H01L24/03 , H01L24/14 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68363 , H01L2221/68372 , H01L2221/68381 , H01L2224/0401 , H01L2224/05025 , H01L2224/13023 , H01L2924/12042 , H01L2924/181 , Y10S438/977 , H01L2924/00
Abstract: A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer.
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5.
公开(公告)号:US09343432B2
公开(公告)日:2016-05-17
申请号:US14094996
申请日:2013-12-03
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chung-Sun Lee , Jung-Hwan Kim , Tae-Hong Kim , Hyun-Jung Song , Sun-Pil Youn
CPC classification number: H01L25/0657 , H01L21/563 , H01L23/3128 , H01L23/3135 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/97 , H01L25/0655 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/16265 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/45139 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06586 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/05552 , H01L2224/81 , H01L2224/83
Abstract: A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip.
Abstract translation: 公开了一叠半导体芯片,半导体器件和制造方法。 堆叠的半导体芯片可以包括堆叠的第一芯片,第一芯片上的堆叠的第二芯片,导电凸块,均匀的整体底部填充材料和模制材料。 导电凸块可以在第一芯片的上表面和第二芯片的下表面之间延伸。 均匀整体的底部填充材料可以插入在第一芯片和第二芯片之间,封装导电凸块,并且沿着第二芯片的侧壁延伸。 均匀整体的底部填充材料可以具有在与第二芯片的上表面平行的方向上延伸并且位于第二芯片的上表面附近的上表面。 模制材料可以在第一芯片的上表面之上的均匀整体底部填充材料的外侧表面上,其中,从第一横截面轮廓的角度来看,模制材料通过均匀的积分与第二芯片的侧壁分离 底部填充材料,使得模制材料不接触第二芯片的侧壁。
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6.
公开(公告)号:US09276133B2
公开(公告)日:2016-03-01
申请号:US14184262
申请日:2014-02-19
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung-Hwan Kim , Jun-Kyu Yang , Hun-Hyeong Lim , Jae-ho Choi , Ki-Hyun Hwang
IPC: H01L27/115 , H01L29/792 , H01L29/66 , H01L21/28
CPC classification number: H01L29/7926 , H01L21/28282 , H01L27/11582 , H01L29/66833
Abstract: A method of manufacturing a vertical memory device is disclosed. In the method, a plurality of insulation layers and a plurality of first sacrificial layers are alternately stacked on a substrate. A plurality of holes is formed through the plurality of insulation layers and first sacrificial layers. A plasma treatment process is performed to oxidize the first sacrificial layers exposed by the holes. A plurality of second sacrificial layer patterns project from sidewalls of the holes. A blocking layer pattern, a charge storage layer pattern and a tunnel insulation layer pattern are formed on the sidewall of the holes that cover the second sacrificial layer patterns. A plurality of channels is formed to fill the holes. The first sacrificial layers and the second sacrificial layer patterns are removed to form a plurality of gaps exposing a sidewall of the blocking layer pattern. A plurality of gate electrodes is formed to fill the gaps.
Abstract translation: 公开了制造垂直存储器件的方法。 在该方法中,多个绝缘层和多个第一牺牲层交替堆叠在基板上。 通过多个绝缘层和第一牺牲层形成多个孔。 进行等离子体处理工艺以氧化由孔暴露的第一牺牲层。 多个第二牺牲层图案从孔的侧壁突出。 在覆盖第二牺牲层图案的孔的侧壁上形成阻挡层图案,电荷存储层图案和隧道绝缘层图案。 形成多个通道以填充孔。 去除第一牺牲层和第二牺牲层图案以形成暴露阻挡层图案的侧壁的多个间隙。 形成多个栅电极以填充间隙。
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公开(公告)号:US09184232B2
公开(公告)日:2015-11-10
申请号:US14538046
申请日:2014-11-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jung-Hwan Kim , Hun-Hyeoung Leam , Tae-Hyun Kim , Seok-Woo Nam , Hyun Namkoong , Yong-Seok Kim , Tea-Kwang Yu
IPC: H01L29/06 , H01L21/28 , H01L21/762 , H01L21/8234 , H01L27/115 , H01L29/423 , H01L29/66 , H01L29/78
CPC classification number: H01L29/785 , H01L21/28282 , H01L21/308 , H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/1079 , H01L29/42352 , H01L29/66818 , H01L29/66833 , H01L29/7851 , H01L29/7854 , H01L2029/7858
Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
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公开(公告)号:US08962444B2
公开(公告)日:2015-02-24
申请号:US14053913
申请日:2013-10-15
Applicant: Samsung Electronics Co., Ltd
Inventor: Jung-Hwan Kim , Sunggil Kim , HongSuk Kim , Guk-Hyon Yon , Hunhyeong Lim
IPC: H01L21/76 , H01L21/762
CPC classification number: H01L21/76224 , H01L21/28273 , H01L21/32155 , H01L21/764 , H01L27/11524
Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon pattern in a gas including second p-type dopants, forming a dielectric layer and a conductive layer on the thermally treated poly-silicon pattern and the device isolation pattern, etching the conductive layer, the dielectric layer, and the thermally treated poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate respectively.
Abstract translation: 提供制造半导体器件的方法。 该方法包括在衬底上形成掺杂有第一p型掺杂剂的多晶硅层,蚀刻多晶硅层和衬底以形成多晶硅图案和沟槽,从而形成覆盖层的下侧壁的器件隔离图案 沟槽中的多晶硅图案,在包括第二p型掺杂剂的气体中热处理多晶硅图案,在热处理的多晶硅图案和器件隔离图案上形成电介质层和导电层,蚀刻导电 层,电介质层和热处理的多晶硅图案,以分别形成控制栅极,电介质图案和浮置栅极。
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公开(公告)号:US11817424B2
公开(公告)日:2023-11-14
申请号:US17212332
申请日:2021-03-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung-Hwan Kim
IPC: H01L25/065 , H01L23/538 , H01L23/00
CPC classification number: H01L25/0657 , H01L23/5385 , H01L23/5386 , H01L24/14
Abstract: A semiconductor package includes a lower semiconductor chip having a first surface and a second surface, an upper semiconductor chip on the first surface, a first insulating layer between the first surface and the upper semiconductor chip, a second insulating layer between the first insulating layer and the upper semiconductor chip, and a connection structure penetrating the first insulating layer and the second insulating layer and being connected to the lower semiconductor chip and the upper semiconductor chip. The connection structure includes a first connecting portion and a second connecting portion, which are respectively disposed in the first insulating layer and the second insulating layer. A width of the second connecting portion is greater than a width of the first connecting portion. A thickness of the second connecting portion is greater than a thickness of the first connecting portion.
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公开(公告)号:US20210305276A1
公开(公告)日:2021-09-30
申请号:US17076306
申请日:2020-10-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sunggil Kim , Seulye Kim , Jung-Hwan Kim
IPC: H01L27/11582 , H01L27/11556
Abstract: A semiconductor memory device includes a substrate with a cell array region and a connection region, an electrode structure including electrodes stacked on the substrate and having a staircase structure on the connection region, a vertical channel structure on the cell array region to penetrate the electrode structure and electrically connected to the substrate, a dummy structure on the connection region to penetrate the staircase structure, and a first sidewall oxide pattern interposed between the substrate and the dummy structure. The dummy structure includes an upper portion that is on the substrate, a middle portion that is in contact with the first sidewall oxide pattern, and a lower portion that is below the middle portion. With increasing vertical distance from the upper portion, a diameter of the middle portion decreases until it reaches its smallest value and then increases.
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