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    SEMICONDUCTOR PACKAGE
    1.
    发明申请
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20190259737A1

    公开(公告)日：2019-08-22

    申请号：US16134583

    申请日：2018-09-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eun-seok Song ,  Chan-kyung Kim ,  Tae-joo Hwang

    IPC: H01L25/10 ,  H01L23/498 ,  G11C5/06

    Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.

    Semiconductor package
    2.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US10665575B2

    公开(公告)日：2020-05-26

    申请号：US16585123

    申请日：2019-09-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eun-seok Song ,  Chan-kyung Kim ,  Tae-joo Hwang

    IPC: H01L23/495 ,  H01L25/10 ,  H01L23/498 ,  G11C5/06 ,  G11C5/04 ,  H01L23/00

    Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.

    Semiconductor package
    4.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US10475774B2

    公开(公告)日：2019-11-12

    申请号：US16134583

    申请日：2018-09-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eun-seok Song ,  Chan-kyung Kim ,  Tae-joo Hwang

    IPC: H01L23/495 ,  H01L25/10 ,  H01L23/498 ,  G11C5/06 ,  H01L23/00

    Abstract: A semiconductor package includes: a memory sub-package including a first connecting layer and a plurality of memory chips disposed on the first connecting layer; a logic sub-package including a second connecting layer, a controller chip disposed on the second connecting layer, and a buffer chip connected to the controller chip and the plurality of memory chips; and a plurality of inter-package connecting members each of which connects the memory sub-package and the logic sub-package, wherein the buffer chip is connected to the plurality of memory chips via a plurality of first data transfer lines each having a first data transfer rate, the buffer chip is connected to the controller chip via a plurality of second data transfer lines each having a second data transfer rate, and the first data transfer rate is less than the second data transfer rate.

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