公开(公告)号：US20210013324A1

公开(公告)日：2021-01-14

申请号：US17038004

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Jin Bum KIM ,  MunHyeon KIM ,  Hyoung Sub KIM ,  Tae Jin PARK ,  Kwan Heum LEE ,  Chang Woo NOH ,  Maria TOLEDANO LU QUE ,  Hong Bae PARK ,  Si Hyung LEE ,  Sung Man WHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.

公开(公告)号：US20220085161A1

公开(公告)日：2022-03-17

申请号：US17229045

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo NOH ,  Myung Gil KANG ,  Tae Young KIM ,  Geum Jong BAE ,  Keun Hwi CHO

IPC: H01L29/06

Abstract: A semiconductor device includes a substrate, first to sixth nanowires extending in a first direction and spaced apart from each other, first to third gate electrodes extending in a second direction and respectively on first to third regions of the substrate, a first interface layer of a first thickness between the first gate electrode and the second nanowire, a second interface layer of a second thickness between the third gate electrode and the sixth nanowire. The first to third gate electrodes respectively may surround the first and second nanowires, third and fourth nanowires, and fifth and sixth nanowires. A first internal spacer may be on a side wall of at least one of the first to third gate electrodes. In the first direction, a first length of the first nanowire may be smaller than a second length of the third nanowire.

公开(公告)号：US20210104613A1

公开(公告)日：2021-04-08

申请号：US17127230

申请日：2020-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Woo NOH ,  Seung Min SONG ,  Geum Jong BAE ,  Dong Il BAE

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.

公开(公告)号：US20190393315A1

公开(公告)日：2019-12-26

申请号：US16205851

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo NOH ,  Seung Min Song ,  Geum Jong Bae ,  Dong Il Bae

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/06

Abstract: A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.

公开(公告)号：US20190198639A1

公开(公告)日：2019-06-27

申请号：US16037922

申请日：2018-07-17

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Jin Bum KIM ,  MunHyeon KIM ,  Hyoung Sub KIM ,  Tae Jin PARK ,  Kwan Heum LEE ,  Chang Woo NOH ,  Maria TOLEDANO LU QUE ,  Hong Bae PARK ,  Si Hyung LEE ,  Sung Man WHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.