公开(公告)号：US20220085161A1

公开(公告)日：2022-03-17

申请号：US17229045

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo NOH ,  Myung Gil KANG ,  Tae Young KIM ,  Geum Jong BAE ,  Keun Hwi CHO

IPC: H01L29/06

Abstract: A semiconductor device includes a substrate, first to sixth nanowires extending in a first direction and spaced apart from each other, first to third gate electrodes extending in a second direction and respectively on first to third regions of the substrate, a first interface layer of a first thickness between the first gate electrode and the second nanowire, a second interface layer of a second thickness between the third gate electrode and the sixth nanowire. The first to third gate electrodes respectively may surround the first and second nanowires, third and fourth nanowires, and fifth and sixth nanowires. A first internal spacer may be on a side wall of at least one of the first to third gate electrodes. In the first direction, a first length of the first nanowire may be smaller than a second length of the third nanowire.

公开(公告)号：US20200013446A1

公开(公告)日：2020-01-09

申请号：US16428184

申请日：2019-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keun Hwi CHO ,  Seunghan PARK ,  Hyo-Jin KIM ,  Gukil AN

IPC: G11C11/22 ,  H01L27/11502 ,  H01L29/51

Abstract: A semiconductor memory device includes a memory cell array including memory cells, a row decoder connected to the memory cell array through first conductive lines, write drivers and sense amplifiers connected to the memory cell array through second conductive lines, a voltage generator that supplies a first voltage to the row decoder and supplies a second voltage to the write drivers and sense amplifiers, and a data buffer that is connected to the write drivers and sense amplifiers and transfers data between the write drivers and sense amplifiers and an external device. At least one of the row decoder, the write drivers and sense amplifiers, the voltage generator, and the data buffer includes a first ferroelectric capacitor to amplify a voltage.

公开(公告)号：US20240234417A9

公开(公告)日：2024-07-11

申请号：US18379731

申请日：2023-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byeol Hae EOM ,  Byung Ha CHOI ,  Keun Hwi CHO ,  Sung Won KIM ,  Yuri MASUOKA ,  Won Cheol JEONG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device includes a first element separation structure, a second element separation structure, and a third element separation structure sequentially disposed along a first direction and extending in a second direction intersecting the first direction; a first active pattern extending in the first direction between the first element separation structure and the second element separation structure; a second active pattern extending in the first direction between the second element separation structure and the third element separation structure and separated from the first active pattern by the second element separation structure; a first gate electrode extending in the second direction on the first active pattern; and a plurality of second gate electrodes extending in the second direction on the second active pattern, wherein a width of the first active pattern in the second direction is greater than a width of the second active pattern in the second direction.

公开(公告)号：US20240038763A1

公开(公告)日：2024-02-01

申请号：US18486331

申请日：2023-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hwi CHO ,  Sangdeok KWON ,  Dae Sin KIM ,  Dongwon KIM ,  Yonghee PARK ,  Hagju CHO

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/11807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0924 ,  H01L2027/11829 ,  H01L2027/11851 ,  H01L2027/11861 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.

公开(公告)号：US20230112528A1

公开(公告)日：2023-04-13

申请号：US18046518

申请日：2022-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： MYUNG GIL KANG ,  Dong Won KIM ,  Woo Seok PARK ,  Keun Hwi CHO ,  Sung Gi HUR

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction different from the first direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

公开(公告)号：US20210091211A1

公开(公告)日：2021-03-25

申请号：US16857621

申请日：2020-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil KANG ,  Dongwon KIM ,  Minyi KIM ,  Keun Hwi CHO

IPC: H01L29/732 ,  H01L21/8228 ,  H01L21/8238 ,  H01L29/735 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device including a well region in a substrate, an impurity region in the well region, a first active fin on the impurity region, a second active fin on the well region, and a connection pattern penetrating the second active fin and connected to the well region may be provided. The substrate and the impurity region include impurities having a first conductivity type. The well region includes impurities having a second conductivity type different from the first conductivity type. The first active fin includes a plurality of first semiconductor patterns that are spaced apart from each other in a direction perpendicular to a top surface of the substrate. The first semiconductor patterns and the impurity region include impurities having the first conductivity type.

公开(公告)号：US20220352342A1

公开(公告)日：2022-11-03

申请号：US17838573

申请日：2022-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guk Il AN ,  Keun Hwi CHO ,  Dae Won HA ,  Seung Seok HA

IPC: H01L29/51 ,  H01L23/522 ,  H01L27/088 ,  H01L29/78 ,  H01L49/02

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

公开(公告)号：US20220328496A1

公开(公告)日：2022-10-13

申请号：US17541790

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil KANG ,  Seunghun LEE ,  Sangdeok KWON ,  Keun Hwi CHO ,  Sung Gi HUR

IPC: H01L27/11 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a first active pattern on a substrate, a pair of first source/drain patterns on the first active pattern and a first channel pattern between the pair of first source/drain patterns, wherein the first channel pattern includes a plurality of semiconductor patterns that are stacked and spaced apart from each other, a first gate electrode on the first channel pattern, a first gate cutting pattern that is adjacent to the first channel pattern and penetrates the first gate electrode, and a first residual pattern between the first gate cutting pattern and the first channel pattern. The first residual pattern covers an outermost sidewall of at least one semiconductor pattern of the plurality of semiconductor patterns of the first channel pattern. The first gate electrode includes, on an upper portion of the first gate electrode, a first extension that vertically overlaps the first residual pattern.

公开(公告)号：US20210167184A1

公开(公告)日：2021-06-03

申请号：US17176226

申请日：2021-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guk Il AN ,  Keun Hwi CHO ,  Dae Won HA ,  Seung Seok HA

IPC: H01L29/51 ,  H01L27/088 ,  H01L23/522 ,  H01L49/02 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.

公开(公告)号：US20200013870A1

公开(公告)日：2020-01-09

申请号：US16418705

申请日：2019-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungseok HA ,  Gukil AN ,  Keun Hwi CHO ,  Sungmin KIM

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/786

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.