公开(公告)号：US20210320213A1

公开(公告)日：2021-10-14

申请号：US17354605

申请日：2021-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil KANG ,  Dong Won KIM ,  Geum Jong BAE ,  Kwan Young CHUN

IPC: H01L29/786 ,  H01L27/11 ,  H01L29/423 ,  H01L27/092 ,  H01L29/06

Abstract: A semiconductor device is provided. The semiconductor device includes: a first wire pattern disposed on a substrate and extending in a first direction; a first gate electrode surrounding the first wire pattern and extending in a second direction, the first direction intersecting the second direction perpendicularly; a first transistor including the first wire pattern and the first gate electrode; a second wire pattern disposed on the substrate and extending in the first direction; a second gate electrode surrounding the second wire pattern and extending in the second direction; and a second transistor including the second wire pattern and the second gate electrode, wherein a width of the first wire pattern in the second direction is different from a width of the second wire pattern in the second direction.

公开(公告)号：US20190115424A1

公开(公告)日：2019-04-18

申请号：US15964170

申请日：2018-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Seok PARK ,  Seung Min SONG ,  Jung Gil YANG ,  Geum Jong BAE ,  Dong Il BAE

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device including a transistor disposed on a first region of a substrate, the transistor including source/drain regions, a plurality of channel layers spaced apart from each other in a direction perpendicular to an upper surface of the substrate while connecting the source/drain regions, respectively, a gate electrode surrounding each of the plurality of channel layers, and a gate insulator between the gate electrode and the plurality of channel layers; and a non-active component disposed on a second region of the substrate, the non-active component including a fin structure including an a plurality of first semiconductor patterns alternately stacked with a plurality of second semiconductor patterns, an epitaxial region adjacent to the fin structure, a non-active electrode intersecting the fin structure, and a blocking insulation film between the non-active electrode and the fin structure.

公开(公告)号：US20190067490A1

公开(公告)日：2019-02-28

申请号：US15900175

申请日：2018-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Woo Seok PARK ,  Dong Chan SUH ,  Seung Min SONG ,  Geum Jong BAE ,  Dong II BAE

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/08 ,  H01L29/161 ,  H01L29/10

Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.

公开(公告)号：US20180190829A1

公开(公告)日：2018-07-05

申请号：US15647903

申请日：2017-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Min SONG ,  Woo Seok PARK ,  Geum Jong BAE ,  Dong Il BAE ,  Jung Gil YANG

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/78618 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.

公开(公告)号：US20180175070A1

公开(公告)日：2018-06-21

申请号：US15843139

申请日：2017-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Dae SUK ,  Geum Jong BAE ,  Joo Hee JEONG

IPC: H01L27/12 ,  H01L29/06 ,  H01L23/528 ,  H01L29/10 ,  H01L27/02 ,  H01L23/522 ,  H01L21/84 ,  H01L21/306 ,  H01L21/762 ,  H01L21/311 ,  H01L21/18

CPC classification number: H01L27/1211 ,  H01L21/185 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/76251 ,  H01L21/76283 ,  H01L21/84 ,  H01L21/845 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/7391

Abstract: A semiconductor device includes a base substrate, a buried insulating film on the base substrate, a first semiconductor substrate pattern on the buried insulating film, a second semiconductor substrate pattern on the buried insulating film, the second semiconductor substrate pattern being spaced apart from the first semiconductor substrate pattern, a first device pattern on the first semiconductor substrate pattern, a second device pattern on the second semiconductor substrate pattern, the first and second device patterns having different characteristics from each other, an isolating trench between the first semiconductor substrate pattern and the second semiconductor substrate pattern, the isolating trench extending only partially into the buried insulating film, and a lower interlayer insulating film overlying the first device pattern and the second device pattern and filling the isolating trench.

公开(公告)号：US20210104613A1

公开(公告)日：2021-04-08

申请号：US17127230

申请日：2020-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Woo NOH ,  Seung Min SONG ,  Geum Jong BAE ,  Dong Il BAE

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.

公开(公告)号：US20210035976A1

公开(公告)日：2021-02-04

申请号：US16919300

申请日：2020-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeong Han GWON ,  Soo Yeon JEONG ,  Geum Jong BAE ,  Dong Il BAE

IPC: H01L27/092 ,  H01L23/535 ,  H01L29/423

Abstract: A semiconductor device includes a substrate, a first lower pattern and a second lower pattern on the substrate and arranged in a line in a first direction, a first active pattern stack disposed on and spaced apart from the first lower pattern, a second active pattern stack disposed on and spaced apart from the first lower pattern, a fin-cut gate structure disposed on the first lower pattern and overlapping a portion of the first lower pattern, a first gate structure surrounding the first active pattern stack and extending in a second direction crossing the first direction, a second gate structure surrounding the second active pattern stack and extending in the second direction, and a device isolation layer between the first gate structure and the second gate structure and separating the first lower pattern and the second lower pattern.

公开(公告)号：US20200091349A1

公开(公告)日：2020-03-19

申请号：US16435657

申请日：2019-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil KANG ,  Dong Won KIM ,  Geum Jong BAE ,  Kwan Young CHUN

IPC: H01L29/786 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device is provided. The semiconductor device includes: a first wire pattern disposed on a substrate and extending in a first direction; a first gate electrode surrounding the first wire pattern and extending in a second direction, the first direction intersecting the second direction perpendicularly; a first transistor including the first wire pattern and the first gate electrode; a second wire pattern disposed on the substrate and extending in the first direction; a second gate electrode surrounding the second wire pattern and extending in the second direction; and a second transistor including the second wire pattern and the second gate electrode, wherein a width of the first wire pattern in the second direction is different from a width of the second wire pattern in the second direction.

公开(公告)号：US20180342508A1

公开(公告)日：2018-11-29

申请号：US15709023

申请日：2017-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Min KIM ,  Dong Won KIM ,  Geum Jong BAE

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/823431 ,  H01L27/0207 ,  H01L29/6656

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a plurality of fins comprising a first fin, a second fin, a third fin, a fourth fin and a fifth fin, each of the plurality of protruding from the substrate in a first direction, and spaced apart from one another in a second direction that intersects the first direction and a plurality of trenches comprising a first trench, a second trench, a third trench and a fourth trench, each of the plurality of trenches being formed between adjacent fins of the plurality of fins, wherein variation of a first width of the first trench and a third width of the third trench is smaller than a first variation, wherein variation of a second width of the second trench and a fourth width of the fourth trench is smaller than a second variation, and wherein the second variation is greater than the first variation.

公开(公告)号：US20170345946A1

公开(公告)日：2017-11-30

申请号：US15666844

申请日：2017-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Ho LEE ,  Ho Jun KIM ,  Sung Dae SUK ,  Geum Jong BAE

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L29/0665 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66545

Abstract: A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets.