公开(公告)号：US20220036954A1

公开(公告)日：2022-02-03

申请号：US17503952

申请日：2021-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Yeon YU ,  Kui-Han KO ,  Il-Han PARK ,  June-Hong PARK ,  Joo-Yong PARK ,  Joon-Young PARK ,  Bong-Soon LIM

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

Abstract: To program in a nonvolatile memory device including a cell region including first metal pads and a peripheral region including second metal pads and vertically connected to the cell region by the first metal pads and the second metal pads, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.

公开(公告)号：US20190198117A1

公开(公告)日：2019-06-27

申请号：US16141147

申请日：2018-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Yeon YU ,  Kui-Han KO ,  Il-Han PARK ,  June-Hong PARK ,  Joo-Yong PARK ,  Joon-Young PARK ,  Bong-Soon LIM

IPC: G11C16/16 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11556

Abstract: To program in a nonvolatile memory device, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.