中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

4 records (took 0.016 seconds)

    NONVOLATILE MEMORY DEVICE AND METHOD OF PERFORMING AN ERASE OPERATION IN THE SAME
    1.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF PERFORMING AN ERASE OPERATION IN THE SAME 审中-公开

    公开(公告)号：US20190221267A1

    公开(公告)日：2019-07-18

    申请号：US16176117

    申请日：2018-10-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kui-Han KO ,  Jin-Young KIM ,  Bong-Soon LIM ,  Il-Han PARK

    IPC: G11C16/16 ,  G11C16/04

    CPC classification number: G11C16/16 ,  G11C16/0483 ,  H01L27/11556

    Abstract: An erase voltage is applied to channels of a selected string group to erase only the selected string group. A size and a number of the spare blocks for storing meta data are reduced and thus a size of the nonvolatile memory device is reduced by reducing unit capacity of the erase operation through grouping of the cell strings. Lifetime of the nonvolatile memory device is extended by having control over erasing some cell strings and not others. Control of cell strings for erasure includes allowing some control lines to float, in some embodiments. In some embodiments, ground select transistors with different thresholds and appropriately applied voltages are used to control erasure of particular cell strings. In some embodiments, biasing of word lines is applied differently to portions of a particular cell string to only erase a portion of the particular cell string.

    NONVOLATILE MEMORY DEVICE WITH INTERMEDIATE SWITCHING TRANSISTORS AND PROGRAMMING METHOD
    2.
    发明申请
    NONVOLATILE MEMORY DEVICE WITH INTERMEDIATE SWITCHING TRANSISTORS AND PROGRAMMING METHOD 有权

    公开(公告)号：US20220036954A1

    公开(公告)日：2022-02-03

    申请号：US17503952

    申请日：2021-10-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chang-Yeon YU ,  Kui-Han KO ,  Il-Han PARK ,  June-Hong PARK ,  Joo-Yong PARK ,  Joon-Young PARK ,  Bong-Soon LIM

    IPC: G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

    Abstract: To program in a nonvolatile memory device including a cell region including first metal pads and a peripheral region including second metal pads and vertically connected to the cell region by the first metal pads and the second metal pads, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.

    NONVOLATILE MEMORY DEVICES
    3.
    发明申请
    NONVOLATILE MEMORY DEVICES 有权

    公开(公告)号：US20210005268A1

    公开(公告)日：2021-01-07

    申请号：US17023556

    申请日：2020-09-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung-Bum KIM ,  Il-Han PARK ,  Ji-Young LEE ,  Su-Chang JEON

    IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

    Abstract: Nonvolatile memory device includes memory cell region including a first metal pad and a second metal pad, peripheral circuit region including a third metal pad and a fourth metal pad, vertically connected to the memory cell region. The nonvolatile memory device includes a page buffer circuit including page buffers to sense data from selected memory cells, each including two sequential sensing operations to determine one data state, and each of the page buffers including a latch to sequentially store results of the two sequential sensing operations. The nonvolatile memory device includes control circuit in the peripheral circuit region, to control the page buffers to store result of the first read operation, reset the latches after completion of the first read operation, and control the page buffers to perform the second read operation based on a valley determined based on the result of the first read operation.

Patent Agency Ranking