公开(公告)号：US09742600B2

公开(公告)日：2017-08-22

申请号：US14840524

申请日：2015-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinesh P. Nair ,  Ashutosh Deepak Gore ,  Kiran Bynam ,  ChangSoon Park ,  Seokju Yun ,  Young-Jun Hong ,  Manoj Choudhary

IPC: H04L25/06

CPC classification number: H04L25/061

Abstract: Provided is a method of estimating a Direct Current (DC) offset in an Ultra-Low Power (ULP) receiver. The method includes receiving a signal from an output of an Analog to Digital Converter (ADC) in the ULP receiver. The signal includes a correlated variable DC component for at least one of an in-phase arm and a quadrature arm of the ULP receiver. The method also includes estimating a DC offset compensation parameter in a plurality of phases for a plurality of stages based on the received signal such that the estimating includes calculating the DC offset compensation parameter in a magnitude estimation phase for the plurality of stages and calculating the DC offset compensation parameter in a sign estimation phase for the plurality of stages.

公开(公告)号：US10257325B2

公开(公告)日：2019-04-09

申请号：US15016559

申请日：2016-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chandrashekhar Thejaswi Ps ,  Kiran Bynam ,  ChangSoon Park ,  Young-Jun Hong ,  Manoj Choudhary

IPC: H04L29/06 ,  H04L1/16 ,  H04L7/04 ,  H04L5/00 ,  H04L27/26 ,  H04L1/00

Abstract: Provided is a method and apparatus of a receiver. The method and apparatus include generating a macro sequence of a length using a complementary-symmetry property. The method and apparatus also obtain a preamble sequence for a communication mode based on the macro sequence.

公开(公告)号：US09692588B2

公开(公告)日：2017-06-27

申请号：US15204195

申请日：2016-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiran Bynam ,  Sujit Jos ,  PS Chandrashekhar Thejaswi ,  ChangSoon Park ,  Jinesh P. Nair ,  Young-Jun Hong ,  Youngsoo Kim ,  Manoj Choudhary

IPC: H04L7/00 ,  H04L7/04 ,  H04B1/30 ,  H04B1/10 ,  H04L27/06 ,  H04L27/00 ,  H04L7/033 ,  H04B1/707 ,  H04B1/7183 ,  H04L25/00

CPC classification number: H04L7/0079 ,  H04B1/10 ,  H04B1/30 ,  H04B1/707 ,  H04B1/7183 ,  H04L7/0033 ,  H04L7/033 ,  H04L7/041 ,  H04L25/00 ,  H04L27/0014 ,  H04L27/06 ,  H04L27/063 ,  H04L2027/0028 ,  H04L2027/0067

Abstract: A method of performing synchronization in a super regenerative receiver (SRR) includes setting a quench rate of the SRR to a value of 1.5 times a chip rate of an incoming signal, acquiring an expected preamble sequence of an arbitrary sample set among a plurality of possible sample sets, acquiring an expected start frame delimiter (SFD) sequence for all of the possible sample sets to achieve frame synchronization, computing respective correlation metrics for bits of the expected SFD sequence while the expected SFD sequence is acquired for all of the possible sample sets, calculating a decision metric based on the correlation metrics in response to an SFD sequence being detected for one or more of the possible sample sets, and identifying a best sample set for demodulating the incoming signal among all of the possible sample sets based on the decision metric to achieve pulse synchronization.