公开(公告)号：US11728795B2

公开(公告)日：2023-08-15

申请号：US17564915

申请日：2021-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanhee Park ,  Ahreum Kim ,  Minsu Kim

IPC: H03K19/0175 ,  H03K3/356 ,  H01L27/02 ,  G06F30/30

CPC classification number: H03K3/356113 ,  G06F30/30 ,  H01L27/0207 ,  H03K19/0175

Abstract: A voltage level shifter cell, which is configured to convert voltage levels of input signals of multi-bits, includes: a first circuit area including a first voltage level shifter configured to convert a 1-bit first input signal from among the input signals; and a second circuit area including a second voltage level shifter configured to convert a 1-bit second input signal from among the input signals, wherein the first circuit area and the second circuit area share a first N-well to which a first power voltage is applied, and the first circuit area and the second circuit area share a second N-well to which a second power voltage is applied, wherein the first N-well is formed to extend in a first direction, and the first N-well and the second N-well are arranged to overlap in a second direction crossing the first direction.

公开(公告)号：US12002651B2

公开(公告)日：2024-06-04

申请号：US17158231

申请日：2021-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunbae Kim ,  Hyejin Kim ,  Chanhee Park

IPC: H01J37/32

CPC classification number: H01J37/32174 ,  H01J37/32128 ,  H01J37/32146 ,  H01J37/32091 ,  H01J37/32577

Abstract: A wafer processing apparatus includes a chamber, and a voltage waveform generator configured to accelerate plasma ions of the chamber, the voltage waveform generator includes: a pulse circuit configured to apply a chamber voltage, which is a pulse voltage, to the chamber by adjusting a chamber current applied to the chamber; and a slope circuit configured to generate a slope in an on-duty of the chamber voltage, which is the pulse voltage, and the pulse circuit includes a first inductive element configured to store a first internal current.

公开(公告)号：US11705306B2

公开(公告)日：2023-07-18

申请号：US17470337

申请日：2021-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunbae Kim ,  Hyunjae Lee ,  Youngdo Kim ,  Hyejin Kim ,  Sangki Nam ,  Chanhee Park ,  Minho Jung

IPC: H01J37/32

CPC classification number: H01J37/32174 ,  H01J37/32146 ,  H01J2237/002

Abstract: A variable frequency and non-sinusoidal power generator includes a pulse module circuit, a slope module circuit, and first and second cooling systems. The pulse module circuit and the slope module circuit includes control switches, and generates at least one of a output currents and a output voltages by selectively turning on/off the control switches based on control signals. The first and second cooling systems are disposed at first and second sides of the control switches. A bias power having a variable frequency and a non-sinusoidal waveform is generated based on the control signals, at least one of the output currents and the output voltages.

公开(公告)号：US20210407769A1

公开(公告)日：2021-12-30

申请号：US17158231

申请日：2021-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunbae Kim ,  Hyejin Kim ,  Chanhee Park

IPC: H01J37/32

Abstract: A wafer processing apparatus includes a chamber, and a voltage waveform generator configured to accelerate plasma ions of the chamber, the voltage waveform generator includes: a pulse circuit configured to apply a chamber voltage, which is a pulse voltage, to the chamber by adjusting a chamber current applied to the chamber; and a slope circuit configured to generate a slope in an on-duty of the chamber voltage, which is the pulse voltage, and the pulse circuit includes a first inductive element configured to store a first internal current.

公开(公告)号：US11082044B2

公开(公告)日：2021-08-03

申请号：US16845135

申请日：2020-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanhee Park ,  Jongwoo Kim ,  Minsu Kim

IPC: H03K3/00 ,  H03K17/16 ,  H03K19/003 ,  G11C5/14 ,  H03K19/00 ,  H03K17/687

Abstract: An integrated circuit is provided. The integrated circuit includes a power gating circuit configured to receive a power supply voltage from a first power line and to output a first driving voltage to a first virtual power line and a logic circuit electrically connected to the first virtual power line and configured to receive power from the power gating circuit. The power gating circuit includes a first p-type transistor and a first n-type transistor connected in parallel between the first power line and the first virtual power line.