公开(公告)号：US20190027224A1

公开(公告)日：2019-01-24

申请号：US15860891

申请日：2018-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyo-Soo CHOO ,  Ji-Hyun PARK ,  Chi-Weon YOON ,  Moo-Sung KIM

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G05F3/26 ,  G11C16/26

Abstract: A voltage generator of a nonvolatile memory device includes a charging circuit, a current mirror circuit, a discharging circuit and an output circuit. The charging circuit amplifies a difference between a reference voltage and a feedback voltage to generate a first current. The current mirror circuit is connected to the charging circuit and generates a second current based on the first current. The discharging circuit is connected to the current mirror circuit to draw the second current, and discharges the output voltage to a target level by adjusting discharging amount of the second current based on a sensing voltage which reflects a change of the feedback voltage. The output circuit is connected to the current mirror circuit, and provides the output voltage based on the first current and the second current to a first word-line connected to an output node.

公开(公告)号：US20190279720A1

公开(公告)日：2019-09-12

申请号：US16205334

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Wan NAM ,  Dong-Hun KWAK ,  Chi-Weon YOON

IPC: G11C16/16 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11573

Abstract: A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.

公开(公告)号：US20130279260A1

公开(公告)日：2013-10-24

申请号：US13919127

申请日：2013-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chi-Weon YOON ,  Dong-Hyuk CHAE ,  Sang-Wan NAM ,  Sung-Won Yun

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3418

Abstract: A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of the memory cell array and reads stored data from the programmed memory cells, and a control circuit that controls the page buffer and the read-write circuit to program the selected memory cells by loaded the program data from in page buffer and to re-program the selected memory cells by re-loaded the program data in the page buffer.

Abstract translation: 一种非易失性存储器件包括存储单元阵列，该存储单元阵列包括连接到相应的字线和连接到相应位线的列的行中的存储单元，存储程序数据的页缓冲器，用于编程和重新编程的读写电路 将程序数据写入到存储单元阵列的选择的存储单元中，并从编程的存储器单元中读取存储的数据;以及控制电路，其控制页面缓冲器和读写电路，以通过从其中加载程序数据对所选存储单元进行编程 页面缓冲区，并通过重新加载页面缓冲区中的程序数据来重新编程所选择的存储单元。