公开(公告)号：US20190027224A1

公开(公告)日：2019-01-24

申请号：US15860891

申请日：2018-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyo-Soo CHOO ,  Ji-Hyun PARK ,  Chi-Weon YOON ,  Moo-Sung KIM

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G05F3/26 ,  G11C16/26

Abstract: A voltage generator of a nonvolatile memory device includes a charging circuit, a current mirror circuit, a discharging circuit and an output circuit. The charging circuit amplifies a difference between a reference voltage and a feedback voltage to generate a first current. The current mirror circuit is connected to the charging circuit and generates a second current based on the first current. The discharging circuit is connected to the current mirror circuit to draw the second current, and discharges the output voltage to a target level by adjusting discharging amount of the second current based on a sensing voltage which reflects a change of the feedback voltage. The output circuit is connected to the current mirror circuit, and provides the output voltage based on the first current and the second current to a first word-line connected to an output node.

公开(公告)号：US20200211646A1

公开(公告)日：2020-07-02

申请号：US16502744

申请日：2019-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Sung CHO ,  Moo-Sung KIM ,  Seung-You BAEK ,  Jong-Min BAEK ,  Bong-Kil JUNG

IPC: G11C13/00

Abstract: In some example embodiments, a program pulse is applied to a resistive memory cell and a plurality of post pulses are applied to the resistive memory cell at a time point after a relaxation time from a time point when application of the program pulse is finished, the plurality of post pulses having voltage levels that increase sequentially. Programming speed and/or performance of the resistive memory device may be enhanced by accelerating resistance drift of the resistive memory cell using the plurality of post pulses having the voltage levels that increase sequentially.

公开(公告)号：US20140304459A1

公开(公告)日：2014-10-09

申请号：US14210883

申请日：2014-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moo-Sung KIM ,  Byung-Hei JUN

IPC: G06F12/02

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459

Abstract: A multi level cell memory system may include a nonvolatile memory device including a memory cell array configured to store first bit page data and second bit page data, and a page buffer configured to store data to be programmed in the memory cell array; and a memory controller configured to input first bit page data and second bit page data into the page buffer, wherein the memory controller is configured such that the memory controller inputs the first bit page data into the page buffer to temporarily store the first bit page data in a first bit page program operation, and inputs the second bit page data into the page buffer together with the temporarily stored first bit page data in a second bit page program operation.

Abstract translation: 多级单元存储器系统可以包括非易失性存储器件，其包括被配置为存储第一位页数据和第二位页数据的存储单元阵列，以及被配置为存储要被编程在存储单元阵列中的数据的页缓冲器; 以及存储器控制器，被配置为将第一位页数据和第二位页数据输入到页缓冲器中，其中存储器控制器被配置为使得存储器控制器将第一位页数据输入到页缓冲器中以临时存储第一位页数据 在第一位页编程操作中，并且在第二位页编程操作中将第二位页数据与临时存储的第一位页数据一起输入到页缓冲器中。