公开(公告)号：US20170170081A1

公开(公告)日：2017-06-15

申请号：US15231862

申请日：2016-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Yong BYUN ,  Ho-Sung SONG ,  Chi-Wook KIM

IPC: H01L21/66 ,  H01L21/78 ,  G01R31/28 ,  H01L23/544

CPC classification number: H01L22/34 ,  G01R31/2834 ,  G01R31/2856 ,  G01R31/2884 ,  G01R31/2894 ,  G01R31/31713 ,  G01R31/318511 ,  H01L21/78 ,  H01L22/14 ,  H01L22/32 ,  H01L23/544 ,  H01L2223/5446 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor chip from a wafer having a test architecture includes forming a plurality of dies on a wafer, each of the plurality of dies including a semiconductor device, forming at least two common pads commonly coupled to the dies, the at least two common pads being formed in a scribe lane, the scribe lane distinguishing the dies with respect to each other, and simultaneously testing the semiconductor devices at a wafer level, using the at least two common pads.