公开(公告)号：US20190198077A1

公开(公告)日：2019-06-27

申请号：US16290102

申请日：2019-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boyoung SEO ,  Yongkyu Lee ,  Gwanhyeob Koh ,  Choong Jae Lee

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/10 ,  H01L43/08 ,  G11C17/02

CPC classification number: G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10

Abstract: A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

公开(公告)号：US10431276B2

公开(公告)日：2019-10-01

申请号：US16290102

申请日：2019-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boyoung Seo ,  Yongkyu Lee ,  Gwanhyeob Koh ,  Choong Jae Lee

IPC: G11C11/00 ,  G11C17/02 ,  G11C11/16 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22

Abstract: A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

公开(公告)号：US09991308B2

公开(公告)日：2018-06-05

申请号：US15455361

申请日：2017-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choong Jae Lee ,  Oh Kyum Kwon ,  Myoung Kyu Park

IPC: H01L27/146

CPC classification number: H01L27/14645 ,  H01L27/14612 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/1469

Abstract: An image sensor includes a first semiconductor layer having a first semiconductor region and a first insulating region, and a second semiconductor layer under the first semiconductor layer including a second semiconductor region and a second insulating region. The first semiconductor layer includes a first transistor having first source or drain regions in the first semiconductor region and a first gate electrode in the first insulating region, a contact wiring, a first wiring layer electrically connecting the contact wiring and the first transistor, and a first junction region electrically connected to the first wiring layer. The second semiconductor layer includes a second transistor having second source or drain regions in the second semiconductor region and a second gate electrode in the second insulating region, a second wiring layer electrically connecting the contact wiring and the second transistor, and a second junction region electrically connected to the second wiring layer.