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公开(公告)号：US11348504B2
公开(公告)日：2022-05-31
申请号：US17139449
申请日：2020-12-31
发明人： Youngmok Kim , Kyunglyong Kang , Jungu Kang , Boyoung Seo , Yongsang Jeong
IPC分类号： G09G3/20
摘要： A display apparatus includes a display panel; and a display driver integrated circuit (DDI) chip coupled to the display panel, the DDI chip being configured to generate a display driving signal for driving the display panel based on image data. The DDI chip may include: a first embedded memory device embedded in the DDI chip and configured to store compensation data for compensating for electrical and optical characteristics of a plurality of pixels included in the display panel; a timing controller configured to control signals for driving the display panel, and to generate a data control signal based on the image data and the compensation data; and a data driver configured to provide a data voltage to the display panel according to the data control signal. The first embedded memory device may not include static random access memory (SRAM).
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2.发明授权公开(公告)号：US10431276B2
公开(公告)日：2019-10-01
申请号：US16290102
申请日：2019-03-01
发明人： Boyoung Seo , Yongkyu Lee , Gwanhyeob Koh , Choong Jae Lee
摘要： A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.
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公开(公告)号：US20220028928A1
公开(公告)日：2022-01-27
申请号：US17380081
申请日：2021-07-20
发明人： Boyoung Seo , Kangho Lee , Yoonjong Song , Junghyuk Lee
IPC分类号： H01L27/22 , H01L27/112
摘要： A magnetic memory device includes a plurality of first bit lines and a plurality of second bit lines, a plurality of first source lines respectively corresponding to the plurality of first bit lines and a plurality of second source lines respectively corresponding to the plurality of second bit lines, a plurality of first memory cells connected between the plurality of first bit lines and the plurality of first source lines, respectively, in a first region, the plurality of first memory cells respectively including a first memory device and a first selection transistor, and a plurality of second memory cells connected between the plurality of second bit lines and the plurality of second source lines, respectively, in a second region, the plurality of second memory cells respectively including a second memory device and a second selection transistor.
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公开(公告)号：US10515678B2
公开(公告)日：2019-12-24
申请号：US16285295
申请日：2019-02-26
发明人： Boyoung Seo , Seongui Seo , Gwanhyeob Koh , Yongkyu Lee
摘要： A magnetic memory device includes a substrate, a landing pad on the substrate, first and second magnetic tunnel junction patterns disposed on the interlayer insulating layer and spaced apart from the landing pad when viewed from a plan view, and an interconnection structure electrically connecting a top surface of the second magnetic tunnel junction pattern to the landing pad. A distance between the landing pad and the first magnetic tunnel junction pattern is greater than a distance between the first and second magnetic tunnel junction patterns, and a distance between the landing pad and the second magnetic tunnel junction pattern is greater than the distance between the first and second magnetic tunnel junction patterns, when viewed from a plan view.
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公开(公告)号：US10593402B2
公开(公告)日：2020-03-17
申请号：US16243796
申请日：2019-01-09
发明人： Suk-Soo Pyo , Hyuntaek Jung , Taejoong Song , Boyoung Seo
摘要： A nonvolatile memory device includes a first variable resistance element connected to a first bit line, and a first transmission ;ate connected between the first variable resistance element and a first source line. The first transmission gate includes a first insulating layer formed on a well connected to aground voltage, a first n-channel metal oxide semiconductor (NMOS) transistor formed on the first insulating layer and connected to a first word line, a second insulating layer formed on the well, the second insulating layer being in the same layer as the first insulating layer, and a first p-channel metal oxide semiconductor (PMOS) transistor formed on the second insulating layer and connected to a first write word line.
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公开(公告)号：US10192618B2
公开(公告)日：2019-01-29
申请号：US15663416
申请日：2017-07-28
发明人： Suk-Soo Pyo , Hyuntaek Jung , Taejoong Song , Boyoung Seo
IPC分类号： G11C13/00
摘要： An operating method of a nonvolatile memory device includes storing different data in first and second reference cells connected to a word line, checking whether the different data are abnormally stored in the first and second reference cells, and when it is determined that the different data are abnormally stored in the first and second reference cells, swapping the first and second reference cells.
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