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    IMAGE SENSOR
    1.
    发明公开
    IMAGE SENSOR 审中-公开

    公开(公告)号：US20230197755A1

    公开(公告)日：2023-06-22

    申请号：US17965268

    申请日：2022-10-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changyong UM ,  Jeongsoon KANG ,  Jeongjin LEE

    IPC: H01L27/146 ,  H01L23/00

    CPC classification number: H01L27/14634 ,  H01L24/08 ,  H01L27/14636 ,  H01L24/80 ,  H01L27/1469 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896

    Abstract: An image sensor may include a lower device on a lower substrate, an intermediate device on an intermediate substrate on the lower substrate, and an upper device on an upper substrate on the intermediate substrate. The lower device may include a logic transistor. The intermediate device may include at least one transistor. The upper device may include a photodiode and a floating diffusion region. The lower substrate, the intermediate substrate and the upper substrate may be stacked. The intermediate substrate may include a stack of a first semiconductor layer, a silicon oxide layer, and a second semiconductor layer pattern. An insulation pattern fills an opening at least partially defined by one or more inner surfaces of the first semiconductor layer. A buried insulation pattern fills a trench extending through the second semiconductor layer pattern.

    SEMICONDUCTOR DEVICE
    2.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240114700A1

    公开(公告)日：2024-04-04

    申请号：US18448615

    申请日：2023-08-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yongjae LEE ,  Seung Pil KO ,  Kilho LEE ,  Jeongjin LEE

    IPC: H10B61/00 ,  H01L23/00 ,  H01L27/146 ,  H10B80/00

    CPC classification number: H10B61/22 ,  H01L24/08 ,  H01L27/14634 ,  H10B80/00 ,  H01L2224/08145

    Abstract: A semiconductor device includes cell lower conductive lines and peripheral lower conductive lines on a substrate, lower electrode contacts on the cell lower conductive lines, peripheral conductive contacts on the peripheral lower conductive lines, variable resistance patterns horizontally spaced apart from each other on the lower electrode contacts. The lower electrode contacts are respectively connected to the variable resistance patterns. Peripheral conductive lines are horizontally spaced apart from the variable resistance patterns on the peripheral conductive contacts. The peripheral conductive contacts are connected to the peripheral conductive lines. The cell and peripheral lower conductive lines are connected to the lower electrode contacts and the peripheral conductive contacts, respectively. The cell and peripheral lower conductive lines are at the same height. A pitch of the cell lower conductive lines directly adjacent to each other is greater than a pitch of the peripheral lower conductive lines directly adjacent to each other.

    EUV EXPOSURE APPARATUS, AND OVERLAY CORRECTION METHOD AND SEMICONDUCTOR DEVICE FABRICATING METHOD USING THE SAME
    3.
    发明申请
    EUV EXPOSURE APPARATUS, AND OVERLAY CORRECTION METHOD AND SEMICONDUCTOR DEVICE FABRICATING METHOD USING THE SAME 有权

    公开(公告)号：US20210397079A1

    公开(公告)日：2021-12-23

    申请号：US17464826

    申请日：2021-09-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Doogyu LEE ,  Seungyoon LEE ,  Jeongjin LEE ,  Chan HWANG

    IPC: G03F1/24 ,  G03F7/20 ,  H01L21/027

    Abstract: Provided are an extreme ultraviolet (EUV) exposure apparatus for improving an overlay error in a EUV exposure process, and an overlay correction method and a semiconductor device fabricating method using the exposure apparatus. The EUV exposure apparatus includes an EUV light source; a first optical system configured to emit EUV light from the EUV light source to an EUV mask; a second optical system configured to emit EUV light reflected from the EUV mask to a wafer; a mask stage; a wafer stage; and a control unit configured to control the mask stage and the wafer stage, wherein, based on a correlation between a first overlay parameter, which is one of parameters of overlay errors between layers on the wafer, and a second overlay parameter, which is another parameter, the first overlay parameter is corrected through correction of the second overlay parameter.

    METHOD OF CONTROLLING SEMICONDUCTOR PROCESS AND SEMICONDUCTOR PROCESSING APPARATUS
    9.
    发明公开
    METHOD OF CONTROLLING SEMICONDUCTOR PROCESS AND SEMICONDUCTOR PROCESSING APPARATUS 审中-公开

    公开(公告)号：US20240152046A1

    公开(公告)日：2024-05-09

    申请号：US18218246

    申请日：2023-07-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jeongjin LEE ,  Doogyu LEE ,  Seungyoon LEE ,  Chan HWANG

    IPC: G03F1/70 ,  G03F7/00 ,  G03F7/20

    CPC classification number: G03F1/70 ,  G03F7/2004 ,  G03F7/70033 ,  G03F7/70558

    Abstract: A method of controlling semiconductor process includes forming a plurality of sample overlay keys by irradiating a first dose of extreme ultraviolet (EUV) light to a first photoresist layer formed on at least one sample wafer; determining a sample correction parameter for correcting a sample overlay error measured from the plurality of sample overlay keys; updating the sample correction parameter based on a difference between the first dose and a second dose; forming a plurality of main overlay keys by irradiating a second dose of extreme ultraviolet light to a second photoresist layer formed on the sample wafer based on the updated sample correction parameter; determining the main correction parameter based on a main overlay error measured from the plurality of main overlay keys; and performing a photolithography process on a wafer different from the sample wafer based on the main correction parameter.

    OVERLAY CORRECTION METHOD, METHOD OF EVALUATING OVERLAY CORRECTION OPERATION, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE OVERLAY CORRECTION METHOD
    10.
    发明申请
    OVERLAY CORRECTION METHOD, METHOD OF EVALUATING OVERLAY CORRECTION OPERATION, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE OVERLAY CORRECTION METHOD 有权

    公开(公告)号：US20220179302A1

    公开(公告)日：2022-06-09

    申请号：US17392788

    申请日：2021-08-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunjay KANG ,  Chorong PARK ,  Doogyu LEE ,  Seungyoon LEE ,  Jeongjin LEE

    IPC: G03F1/36 ,  G03F1/22

    Abstract: Disclosed are an overlay correction method, a method of evaluating an overlay correction operation, and a method of fabricating a semiconductor device using the overlay correction method. The overlay correction method may include measuring an overlay between center lines of lower and upper patterns on a wafer, fitting each of components of the overlay with a polynomial function to obtain first fitting quantities, and summing the first fitting quantities to construct a correction model. The components of the overlay may include overlay components, which are respectively measured in two different directions parallel to a top surface of a reticle. The highest order of the polynomial function may be determined as an order, which minimizes a difference between the polynomial function and each of the components of the overlay or corresponds to an inflection point in a graph of the difference with respect to the highest order of the polynomial function.

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