公开(公告)号：US20240213146A1

公开(公告)日：2024-06-27

申请号：US18352552

申请日：2023-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNGJUNE KIM ,  BYUNGYUN KANG ,  DONGHYUN KIM

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/0924

Abstract: A semiconductor device according to the disclosure includes: a substrate including a first side and a second side opposite each other with a thickness therebetween, a first wire disposed on the first side of the substrate, a first dummy wire disposed on the first side of the substrate and spaced apart from the first wire, a second wire disposed on the second side of the substrate, a second dummy wire disposed on the second side of the substrate and spaced apart from the second wire, a through via passing through the substrate and connecting the first wire and the second wire, and a plurality of dummy through vias passing through the substrate , wherein the plurality of dummy through vias are laterally offset and physically separated from the first wire and the second wire, wherein a center of at least one of the plurality of dummy through vias is laterally offset from an edge of at least one of the first dummy wire and the second dummy wire.

公开(公告)号：US20240375227A1

公开(公告)日：2024-11-14

申请号：US18657146

申请日：2024-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHYUN KIM ,  JONGSEONG KO ,  DAEYONG KIM ,  JISU KIM ,  PYUNGKANG KIM ,  KIHONG PARK ,  JUNGJUN PARK ,  JUNGJOON PARK ,  JOOYOUNG PARK ,  JUNHYEOK PARK ,  HOSEOK SONG ,  CHIHO AHN ,  KONGWOO LEE ,  HYUNYOUNG LEE ,  CHUYOUNG CHOUNG ,  JEONGMIN HWANG

IPC: B23P19/06 ,  B23Q5/10

Abstract: A fastening device includes: a support portion including a first end portion, and a second end portion, and a central portion between the first and second end portions; a first pulley, a second pulley, and a third pulley rotatably disposed on the central portion, the first end portion, and the second end portion, respectively; a first connection portion and a second connection portion respectively rotatably disposed on the first and second end portions and respectively connected to the second and third pulleys; a first fastening tool and a second fastening tool respectively connected to the first and second connection portions; and a motor connected to the first pulley, wherein a force generated by the motor and provided to the first pulley is at least partially transmitted to the second and third pulleys to vary a distance between the first and second fastening tools.

公开(公告)号：US20160043197A1

公开(公告)日：2016-02-11

申请号：US14820564

申请日：2015-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHEOL KIM ,  DONGHYUN KIM ,  MYEONGCHEOL KIM ,  DAEYONG KIM ,  CHULSUNG KIM

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L29/6681 ,  H01L21/31116 ,  H01L21/76897 ,  H01L29/6656

Abstract: Provided are a semiconductor device and a fabrication method thereof. The semiconductor device may include a fin-shaped active pattern and a gate electrode provided on a substrate, first and second spacers provided on a sidewall of the gate electrode, impurity regions provided at both sides of the gate electrode, a contact plug electrically connected to one of the impurity regions, and a third spacer enclosing the contact plug and having a top surface positioned at substantially the same level as a top surface of the contact plug.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括鳍形有源图案和设置在基板上的栅电极，设置在栅电极的侧壁上的第一和第二间隔物，设置在栅电极两侧的杂质区，电连接到 一个杂质区，以及包围该接触插塞的第三间隔件，并且具有位于该接触插塞顶表面基本相同高度的顶表面。

公开(公告)号：US20140374830A1

公开(公告)日：2014-12-25

申请号：US14313435

申请日：2014-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HEEDON JEONG ,  JAE YUP CHUNG ,  HEESOO KANG ,  DONGHYUN KIM ,  SANGHYUK HONG ,  SOOHUN HONG

IPC: H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/7855

Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.

Abstract translation: 半导体器件包括具有短边和短边的鳍片区域，第一场绝缘层，其包括比鳍片区域的顶表面低的顶表面，并且与鳍片区域的短边的侧表面相邻;第二场绝缘层，包括 与翅片区域相比较靠近散热片区域的长边侧表面的顶表面，第一场绝缘层上的蚀刻阻挡图案，鳍状区域上的第一栅极和第二场绝缘层， 面对翅片区域的顶表面和翅片区域的长边的侧表面。 第二栅极位于与第一场绝缘层重叠的蚀刻阻挡图案上。 源极/漏极区在第一栅极和第二栅极之间，与蚀刻阻挡图案接触。