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公开(公告)号：US12236104B2
公开(公告)日：2025-02-25
申请号：US17889117
申请日：2022-08-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dae-Jeong Kim , Tae-Kyeong Ko , Nam Hyung Kim , Do-Han Kim , Deokho Seo , Ho-Young Lee , Insu Choi
Abstract: An operation method of a memory controller, which is configured to control a memory module including a plurality of memory devices and at least one error correction code (ECC) device, is provided. The method includes reading a data set including user data stored in the plurality of memory devices and ECC data stored in the at least one ECC device, based on a read command and a first address, and writing uncorrectable data in a memory area, which is included in each of the plurality of memory devices and the at least one ECC device and corresponds to the first address, when an error of the user data is not corrected based on the ECC data.
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公开(公告)号：US11915782B2
公开(公告)日：2024-02-27
申请号：US17407585
申请日：2021-08-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chang Min Lee , Nam Hyung Kim , Dae Jeong Kim , Do Han Kim , Min Su Kim , Deok Ho Seo , Won Jae Shin , Yong Jun Yu , Il Gyu Jung , In Su Choi
CPC classification number: G11C7/1063 , G11C7/109 , G11C7/1012 , G11C7/14 , G11C8/18
Abstract: An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.
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公开(公告)号：US11487613B2
公开(公告)日：2022-11-01
申请号：US17105821
申请日：2020-11-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wonjae Shin , Nam Hyung Kim , Dae-Jeong Kim , Do-Han Kim , Minsu Kim , Deokho Seo , Yongjun Yu , Changmin Lee , Insu Choi
Abstract: A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.
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Patent Agency Ranking
公开(公告)号：US20210373996A1
公开(公告)日：2021-12-02
申请号：US17177415
申请日：2021-02-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Deok Ho Seo , Nam Hyung Kim , Dae-Jeong Kim , Do-Han Kim , Min Su Kim , Won Jae Shin , Yong Jun Yu , Chang Min Lee , Il Gyu Jung , In Su Choi
IPC: G06F11/10 , G11C11/406
Abstract: A memory module includes a memory device configured to receive a first refresh command from a host, and perform a refresh operation in response to the first refresh command during a refresh time, and a computing unit configured to detect the first refresh command provided from the host to the memory device, and write a first error pattern at a first address of the memory device during the refresh time.
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公开(公告)号：US11631443B2
公开(公告)日：2023-04-18
申请号：US17480359
申请日：2021-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yong Jun Yu , Nam Hyung Kim , Do-Han Kim , Min Su Kim , Deok Ho Seo , Won Jae Shin , Chang Min Lee , Il Gyu Jung , In Su Choi
Abstract: A semiconductor device including a memory device which has improved reliability is provided. The semiconductor device comprises at least one data pin configured to transfer a data signal, at least one command address pin configured to transfer a command and an address, at least one serial pin configured to transfer a serial data signal, and processing circuitry connected to the at least one data pin and the at least one serial pin. The processing circuitry is configured to receive the data signal from outside through the at least one data pin, and the processing circuitry is configured to output the serial data signal through the at least one serial pin in response to the received data signal.
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公开(公告)号：US11531585B2
公开(公告)日：2022-12-20
申请号：US17177415
申请日：2021-02-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Deok Ho Seo , Nam Hyung Kim , Dae-Jeong Kim , Do-Han Kim , Min Su Kim , Won Jae Shin , Yong Jun Yu , Chang Min Lee , Il Gyu Jung , In Su Choi
IPC: G06F11/10 , G11C29/42 , G11C29/52 , G11C11/406 , G11C29/10
Abstract: A memory module includes a memory device configured to receive a first refresh command from a host, and perform a refresh operation in response to the first refresh command during a refresh time, and a computing unit configured to detect the first refresh command provided from the host to the memory device, and write a first error pattern at a first address of the memory device during the refresh time.
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公开(公告)号：US11887692B2
公开(公告)日：2024-01-30
申请号：US17535861
申请日：2021-11-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wonjae Shin , Nam Hyung Kim , Dae-Jeong Kim , Do-Han Kim , Deokho Seo , Insu Choi
CPC classification number: G11C7/222 , G11C7/1009 , G11C7/109 , G11C7/1063 , G11C8/18
Abstract: An operation method of a memory device, having a plurality of memory cells, includes receiving a partial write command, which includes a partial write enable signal (PWE) and a plurality of mask signals, during a command/address input interval. A data strobe signal is received through a data strobe line after receiving the partial write command Data is received through a plurality of data lines in synchronization with the data strobe signal during a data input interval. A part of the data is stored in the plurality of memory cells based on the plurality of mask signals, in response to the partial write enable signal, during a data write interval.
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公开(公告)号：US11321177B2
公开(公告)日：2022-05-03
申请号：US17108331
申请日：2020-12-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minsu Kim , Nam Hyung Kim , Dae-Jeong Kim , Do-Han Kim , Deokho Seo , Wonjae Shin , Yongjun Yu , Changmin Lee , Insu Choi
IPC: G06F11/10 , G11C11/4091 , G11C11/408
Abstract: A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.
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