公开(公告)号：US20150113342A1

公开(公告)日：2015-04-23

申请号：US14463130

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bong-Kil JUNG ,  Dae-Seok BYEON

IPC: G11C29/50 ,  G06F11/26

CPC classification number: G06F11/26 ,  G11C8/14 ,  G11C16/3418 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0411

Abstract: A method of operating a memory system includes reading data of first memory cells, the first memory cells being connected to a first wordline from among a plurality of wordlines, the plurality of wordlines including one or more dummy wordlines and one or more normal wordlines; determining whether the first wordline is one of the one or more dummy wordlines by determining, based on the read data, a number of the first memory cells having a first threshold voltage state, the one or more dummy wordlines being wordlines the memory cells of which have been programmed with dummy data, the one or more normal wordlines being wordlines that are not dummy wordlines; and performing a repair algorithm for correcting an error in the read data, selectively according to a result of the determination.

Abstract translation: 一种操作存储器系统的方法包括读取第一存储器单元的数据，第一存储器单元从多个字线中连接到第一字线，多个字线包括一个或多个虚拟字线和一个或多个正常字线; 通过基于读取的数据确定具有第一阈值电压状态的第一存储器单元的数量，确定第一字线是否是一个或多个虚拟字线中的一个，一个或多个虚拟字线是其存储单元的字母 已经用伪数据编程，一个或多个正常字线是不是伪字线的字线; 以及根据确定的结果选择性地执行用于校正读取数据中的错误的修复算法。

公开(公告)号：US20200118629A1

公开(公告)日：2020-04-16

申请号：US16422213

申请日：2019-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Kyu KIM ,  Young-Sun MIN ,  Dae-Seok BYEON ,  Ho-Kil LEE

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/32

Abstract: A high voltage switch circuit includes a first transistor, a first depletion mode transistor, a level shifter, a control signal generator, a second transistor and a second depletion mode transistor. The first transistor transmits the second driving voltage to an output terminal in response to a first gate signal. The first depletion mode transistor transmits the second driving voltage to the first transistor in response to feedback from the output terminal. The control signal generator generates first and second control signals in response to a level-shifted enable signal. The second transistor has a gate electrode connected to the first voltage and is turned on and off in response to the second control signal at a first end of the second transistor. The second depletion mode transistor is connected between a second end of the second transistor and the output terminal, and has a gate electrode receiving the first control signal.