公开(公告)号：US20230138601A1

公开(公告)日：2023-05-04

申请号：US17957532

申请日：2022-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Wan NAM ,  Hyunggon KIM ,  Bong-Kil JUNG ,  Younho HONG ,  Juseong HWANG

IPC: G11C16/08

Abstract: Disclosed is a memory device includes a memory block that is connected with a plurality of wordlines, a voltage generating circuit configured to output a first non-selection voltage through a plurality of driving lines, and an address decoding circuit configured to connect the plurality of driving lines with unselected wordlines of the plurality of wordlines. During a wordline setup period for the plurality of wordlines, the voltage generating circuit floats first driving lines corresponding to first unselected wordlines of the unselected wordlines from among the plurality of driving lines when the first unselected wordlines reach a first target level, and floats second driving lines corresponding to second unselected wordlines of the unselected wordlines from among the plurality of driving lines when the second unselected wordlines reach a second target level different from the first target level.

公开(公告)号：US20150113342A1

公开(公告)日：2015-04-23

申请号：US14463130

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bong-Kil JUNG ,  Dae-Seok BYEON

IPC: G11C29/50 ,  G06F11/26

CPC classification number: G06F11/26 ,  G11C8/14 ,  G11C16/3418 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0411

Abstract: A method of operating a memory system includes reading data of first memory cells, the first memory cells being connected to a first wordline from among a plurality of wordlines, the plurality of wordlines including one or more dummy wordlines and one or more normal wordlines; determining whether the first wordline is one of the one or more dummy wordlines by determining, based on the read data, a number of the first memory cells having a first threshold voltage state, the one or more dummy wordlines being wordlines the memory cells of which have been programmed with dummy data, the one or more normal wordlines being wordlines that are not dummy wordlines; and performing a repair algorithm for correcting an error in the read data, selectively according to a result of the determination.

Abstract translation: 一种操作存储器系统的方法包括读取第一存储器单元的数据，第一存储器单元从多个字线中连接到第一字线，多个字线包括一个或多个虚拟字线和一个或多个正常字线; 通过基于读取的数据确定具有第一阈值电压状态的第一存储器单元的数量，确定第一字线是否是一个或多个虚拟字线中的一个，一个或多个虚拟字线是其存储单元的字母 已经用伪数据编程，一个或多个正常字线是不是伪字线的字线; 以及根据确定的结果选择性地执行用于校正读取数据中的错误的修复算法。

公开(公告)号：US20230126012A1

公开(公告)日：2023-04-27

申请号：US17866904

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bong-Kil JUNG ,  Sang-Wan NAM ,  Jong Min BAEK ,  Min Ki JEON ,  Woo Chul JUNG ,  Yoon-Hee CHOI

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a first voltage generator configured to generate a word line operating voltage for each word line of the memory cell array, a second voltage generator configured to generate a bit line operating voltage of the memory cell array, and a temperature unit configured to determine, from a temperature range table, a temperature range for a temperature code according to a real-time temperature of the memory cell array, and to adjust a power supply voltage of the first or second voltage generator based on a selection signal mapped to the determined temperature range.

公开(公告)号：US20210343352A1

公开(公告)日：2021-11-04

申请号：US17134968

申请日：2020-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung CHO ,  Bong-Kil JUNG ,  Hangil JEONG

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/30 ,  G11C16/32

Abstract: An operating method of a nonvolatile memory device includes receiving, at the nonvolatile memory device, a suspend command, suspending, at the nonvolatile memory device, a program operation being performed, in response to the suspend command, receiving, at the nonvolatile memory device, a resume command, and resuming, at the nonvolatile memory device, the suspended program operation in response to the resume command. The program operation includes program loops, each of which includes a bit line setup interval, a program interval, and a verify interval. In the program interval of each of the program loops, a level of a program voltage to be applied to selected memory cells of the nonvolatile memory device increases as much as a first voltage. A difference between a level of the program voltage finally applied s suspend and a level of the program voltage applied first after resume is different from the first voltage.

公开(公告)号：US20220035597A1

公开(公告)日：2022-02-03

申请号：US17222494

申请日：2021-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-Kil JUNG

IPC: G06F7/50 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/535

Abstract: A semiconductor memory device is provided, comprising: a memory cell region including a memory cell array; and a peripheral circuit region which at least partially overlaps the memory cell region and includes control logic configured to control operation of the memory cell array, wherein the control logic includes a state machine configured to output a plurality of state signals responsive to operation commands of the memory cell region, the plurality of state signals including a first state signal output from a first output terminal, and a second state signal output from a second output terminal different from the first output terminal, a logical sum calculator configured to perform a logical sum calculation based on at least one of the first state signal or the second state signal, and an accumulation circuit configured to receive an output of the logical sum calculator as a clock signal, and that outputs a toggle signal to one probing pad in response to the clock signal, the accumulation circuit being connected to the probing pad through a Through Hole Via (THV) penetrating the memory cell region.

公开(公告)号：US20200211646A1

公开(公告)日：2020-07-02

申请号：US16502744

申请日：2019-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Sung CHO ,  Moo-Sung KIM ,  Seung-You BAEK ,  Jong-Min BAEK ,  Bong-Kil JUNG

IPC: G11C13/00

Abstract: In some example embodiments, a program pulse is applied to a resistive memory cell and a plurality of post pulses are applied to the resistive memory cell at a time point after a relaxation time from a time point when application of the program pulse is finished, the plurality of post pulses having voltage levels that increase sequentially. Programming speed and/or performance of the resistive memory device may be enhanced by accelerating resistance drift of the resistive memory cell using the plurality of post pulses having the voltage levels that increase sequentially.

公开(公告)号：US20190096491A1

公开(公告)日：2019-03-28

申请号：US15950757

申请日：2018-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bong-Kil JUNG

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/08 ,  G11C16/04 ,  G06F11/10

CPC classification number: G11C16/26 ,  G06F11/1008 ,  G06F11/1068 ,  G11C7/1006 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  G11C2211/5642

Abstract: A nonvolatile memory device includes a plurality of memory cells and a page buffer including a plurality of page buffer units each connected to the plurality of memory cells through one bit line of a plurality of bit lines and configured to generate output data based on data states of the plurality of memory cells. A first page buffer unit of the plurality of page buffer units includes first to third latches which latch first to third read data at first to third time points, respectively by developing a voltage level of the sensing node, and a fourth latch which generates a fourth read data based on the second and third read data. The first page buffer unit is configured to selectively output the fourth read data as the output data, depending on whether an error correction of the first read data is possible.