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公开(公告)号：US10198387B2
公开(公告)日：2019-02-05
申请号：US15163310
申请日：2016-05-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Il-Hyung Chung , Cheol-Ho Lee , Dong-Ho Yu , Dae-Woong Kim
Abstract: An electronic device and a method for changing modes according to external devices connected through a universal serial bus (USB) and controlling the strength of signals communicated according to changed modes are provided. The method includes detecting a connection with an external device corresponding to booting of the electronic device, determining a mode of the electronic device according to the detected connection with the external device, varying a characteristic setting of an input output (IO) buffer to a certain strength corresponding to the determined mode, and communicating a signal at a strength corresponding to the varied setting.
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公开(公告)号：US20140164860A1
公开(公告)日：2014-06-12
申请号：US14096474
申请日：2013-12-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dae-Woong Kim
IPC: G01R31/317
CPC classification number: G01R31/318536 , G01R31/318552 , G01R31/318555
Abstract: An on-chip clock controller includes a clock-control chain configured to shift first clock-control bits in serial and output the first clock-control bits to a first clock domain in parallel in response to a clock-control scan clock provided from outside of a chip, and a first domain clock generator, the first domain clock generator configured, during a test mode, to generate a first internal clock by selectively outputting a first data scan clock provided from outside of the chip or a first functional clock generated from inside of the chip.
Abstract translation: 片上时钟控制器包括时钟控制链，其被配置为串行移位第一时钟控制位并且响应于从外部提供的时钟控制扫描时钟并行地将第一时钟控制位输出到第一时钟域 芯片和第一域时钟发生器，第一域时钟发生器在测试模式期间被配置为通过选择性地输出从芯片外部提供的第一数据扫描时钟或从内部产生的第一功能时钟来产生第一内部时钟 的芯片。
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3.发明授权公开(公告)号：US09692617B2
公开(公告)日：2017-06-27
申请号：US15193203
申请日：2016-06-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Il-Hyung Chung , Cheol-Ho Lee , Dae-Woong Kim
CPC classification number: H04L25/03031 , H04B1/40 , H04L25/03878
Abstract: The present disclosure relates to an improvement in the quality of a transmitted signal, and more particularly, to an electronic apparatus and a method which are provided with a passive equalizer improving the quality of a transmitted signal when a signal is transmitted/received to/from an external apparatus, and a system for the same. The present disclosure provides a signal transmission system for improving the quality of a transmitted signal. The signal transmission system may include a transmitter that transmits a signal; a receiver that receives the signal from the transmitter; a channel that is formed between the transmitter and the receiver and transmits the signal delivered by the transmitter; and a passive equalizer that is formed between the transmitter and the receiver and controls the signal so as to have a higher impedence than a predetermined impedance at a lower frequency than a predetermined frequency of the signal.
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公开(公告)号：US09222979B2
公开(公告)日：2015-12-29
申请号：US14096474
申请日：2013-12-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dae-Woong Kim
IPC: G01R31/28 , G01R31/3185
CPC classification number: G01R31/318536 , G01R31/318552 , G01R31/318555
Abstract: An on-chip clock controller includes a clock-control chain configured to shift first clock-control bits in serial and output the first clock-control bits to a first clock domain in parallel in response to a clock-control scan clock provided from outside of a chip, and a first domain clock generator, the first domain clock generator configured, during a test mode, to generate a first internal clock by selectively outputting a first data scan clock provided from outside of the chip or a first functional clock generated from inside of the chip.
Abstract translation: 片上时钟控制器包括时钟控制链，其被配置为串行移位第一时钟控制位并且响应于从外部提供的时钟控制扫描时钟并行地将第一时钟控制位输出到第一时钟域 芯片和第一域时钟发生器，第一域时钟发生器在测试模式期间被配置为通过选择性地输出从芯片外部提供的第一数据扫描时钟或从内部产生的第一功能时钟来产生第一内部时钟 的芯片。
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