Semiconductor memory devices and methods of manufacturing the same
    1.
    发明授权
    Semiconductor memory devices and methods of manufacturing the same 有权
    半导体存储器件及其制造方法

    公开(公告)号:US09111619B2

    公开(公告)日:2015-08-18

    申请号:US13652849

    申请日:2012-10-16

    Abstract: A semiconductor device includes a bit line, a first cell string and a second cell string. The first cell string includes a first selecting transistor connected to the bit line in series and having a threshold voltage greater than a first reference voltage, a second selecting transistor having a threshold voltage smaller than a second reference voltage, cell transistors and a ground selecting transistor. The second cell string includes a third selecting transistor connected to the bit line in series and having a threshold voltage smaller than the first reference voltage, a fourth selecting transistor having a threshold voltage greater than the second reference voltage, cell transistors and a ground selecting transistor. A channel region of the first selecting transistor has an enhancement mode and a first conductive type. A channel region of the third selecting transistor has a depletion mode and a second conductive type.

    Abstract translation: 半导体器件包括位线,第一单元串和第二单元串。 第一单元串包括串联连接到位线并且具有大于第一参考电压的阈值电压的第一选择晶体管,具有小于第二参考电压的阈值电压的第二选择晶体管,单元晶体管和接地选择晶体管 。 第二单元串包括串联连接到位线并且具有小于第一参考电压的阈值电压的第三选择晶体管,具有大于第二参考电压的阈值电压的第四选择晶体管,单元晶体管和接地选择晶体管 。 第一选择晶体管的沟道区具有增强模式和第一导电类型。 第三选择晶体管的沟道区具有耗尽模式和第二导电类型。

    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    半导体存储器件及其制造方法

    公开(公告)号:US20130094287A1

    公开(公告)日:2013-04-18

    申请号:US13652849

    申请日:2012-10-16

    Abstract: A semiconductor device includes a bit line, a first cell string and a second cell string. The first cell string includes a first selecting transistor connected to the bit line in series and having a threshold voltage greater than a first reference voltage, a second selecting transistor having a threshold voltage smaller than a second reference voltage, cell transistors and a ground selecting transistor. The second cell string includes a third selecting transistor connected to the bit line in series and having a threshold voltage smaller than the first reference voltage, a fourth selecting transistor having a threshold voltage greater than the second reference voltage, cell transistors and a ground selecting transistor. A channel region of the first selecting transistor has an enhancement mode and a first conductive type. A channel region of the third selecting transistor has a depletion mode and a second conductive type.

    Abstract translation: 半导体器件包括位线,第一单元串和第二单元串。 第一单元串包括串联连接到位线并且具有大于第一参考电压的阈值电压的第一选择晶体管,具有小于第二参考电压的阈值电压的第二选择晶体管,单元晶体管和接地选择晶体管 。 第二单元串包括串联连接到位线并且具有小于第一参考电压的阈值电压的第三选择晶体管,具有大于第二参考电压的阈值电压的第四选择晶体管,单元晶体管和接地选择晶体管 。 第一选择晶体管的沟道区具有增强模式和第一导电类型。 第三选择晶体管的沟道区具有耗尽模式和第二导电类型。

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