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公开(公告)号：US11670355B2
公开(公告)日：2023-06-06
申请号：US17406511
申请日：2021-08-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minsu Kim , Namhyung Kim , Daejeong Kim , Dohan Kim , Chanik Park , Deokho Seo , Wonjae Shin , Changmin Lee , Ilguy Jung , Insu Choi
IPC: G11C7/00 , G11C11/406 , G11C11/4076 , G11C11/4096
CPC classification number: G11C11/40615 , G11C11/4076 , G11C11/4096 , G11C11/40618
Abstract: Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.
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公开(公告)号：US11082612B2
公开(公告)日：2021-08-03
申请号：US16763261
申请日：2018-11-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaeho Kim , Jinmin Bang , Dohan Kim , Changwoo Lee , Kwanho Kim , Jonghoon Won , Kihuk Lee
Abstract: An electronic device according to various embodiments of the present invention comprises a processor and an image sensor module electrically connected to the processor, wherein: the image sensor module comprises an image sensor and a control circuit, which is electrically connected to the image sensor and is connected to the processor by an interface; the control circuit is set so as not to compress at least one image acquired from the image sensor according to a first readout speed, but to transmit the same to the processor, and to compress at least one image acquired from the image sensor according to a second readout speed that is faster than the first readout speed and to transmit the same to the processor; and the processor can be set so as to acquire a first image set by using the image sensor according to a predetermined readout speed, compare at least two images included in the first image set, set, as either the first readout speed or the second readout speed, the readout speed corresponding to the image sensor on the basis of the result of the comparison of the at least two images included in the first image set, and acquire a second image set according to either the set first readout speed or second readout speed, by using the image sensor. Additional various embodiments are possible.
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公开(公告)号：US11089233B2
公开(公告)日：2021-08-10
申请号：US16704160
申请日：2019-12-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Changwoo Lee , Dohan Kim , Jinmin Bang
Abstract: An electronic device is provided that includes an image sensor of first pixels receiving light for a first duration and second pixels receiving light for a shorter second duration, and a processor to acquire first and second raw data including first long pixel values through the first pixels and first short pixel values through the second pixels, second long pixel values through the first pixels and second short pixel values through the second pixels, and third raw data based on the first and second raw data. The third raw data includes third long pixel values and third short pixel values, and each of the third long pixel values is an average value of a first and a second long pixel value and each of the third short pixel values is a value obtained by gamma correcting a sum of a first and a second short pixel value.
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公开(公告)号：US20250013746A1
公开(公告)日：2025-01-09
申请号：US18534135
申请日：2023-12-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongha KIM , Seungki Hong , Youngjae Park , Dohan Kim
Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an error check and scrub (ECS) circuit, a row hammer management circuit and a refresh control circuit. The ECC engine generates an error generation signal based on a result of an ECC decoding. The ECS circuit generates scrubbing addresses and outputs at least one of the scrubbing addresses as an error address based on the error generation signal. The row hammer management circuit stores an error flag with a first logic level in count cells, compares counted values with different reference number of times based on a logic level of the error flag and outputs a hammer address. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to the memory cell row corresponding to the hammer address.
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5.发明授权公开(公告)号：US12141478B2
公开(公告)日：2024-11-12
申请号：US17932734
申请日：2022-09-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Deokho Seo , Taekyeong Ko , Namhyung Kim , Daejeong Kim , Dohan Kim , Hoyoung Lee , Insu Choi
Abstract: A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.
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Patent Agency Ranking
公开(公告)号：US11721408B2
公开(公告)日：2023-08-08
申请号：US17388238
申请日：2021-07-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Daejeong Kim , Namhyung Kim , Dohan Kim , Deokho Seo , Wonjae Shin , Insu Choi
CPC classification number: G11C29/42 , G06F11/1068 , G11C29/50004 , G11C2029/5004
Abstract: A memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into multiple regions. The test controller is configured to perform a parallel bit test (PBT) on the plurality of memory cells, where the test controller selects fail data including a fail data bit among internal data output from the multiple regions during the PBT, and outputs the fail data via a data input/output signal line to the outside of the memory device.
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公开(公告)号：US11671704B2
公开(公告)日：2023-06-06
申请号：US17521346
申请日：2021-11-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwanho Kim , Dohan Kim , Changwoo Lee
IPC: H04N23/667 , H04N23/45 , H04N23/63 , H04N23/69 , H04N23/57
CPC classification number: H04N23/667 , H04N23/45 , H04N23/632 , H04N23/69 , H04N23/57
Abstract: Various embodiments may provide an electronic device including a memory, a first image sensor circuit, a second image sensor circuit, and at least one processor, operatively connected to the first image sensor circuit and the second image sensor circuit, configured to control the first image sensor circuit to output first frame data associated with a first field of view at a first frame rate from a first time point to a second time point, and store the first frame data in the memory, control the second image sensor circuit to output second frame data associated with a second field of view at the first frame rate from a third time point after the second time point to a fourth time point, and store the second frame data in the memory, obtain the stored first frame data and the stored second frame data from the memory.
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公开(公告)号：US11610624B2
公开(公告)日：2023-03-21
申请号：US17474666
申请日：2021-09-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minsu Kim , Namhyung Kim , Daejeong Kim , Dohan Kim , Chanik Park , Deokho Seo , Wonjae Shin , Changmin Lee , Ilguy Jung , Insu Choi
IPC: G11C11/406
Abstract: Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row.
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公开(公告)号：US20220215871A1
公开(公告)日：2022-07-07
申请号：US17406511
申请日：2021-08-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minsu Kim , Namhyung Kim , Daejeong Kim , Dohan Kim , Chanik Park , Deokho Seo , Wonjae Shin , Changmin Lee , Ilguy Jung , Insu Choi
IPC: G11C11/406 , G11C11/4076 , G11C11/4096
Abstract: Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.
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公开(公告)号：US11240457B2
公开(公告)日：2022-02-01
申请号：US16632498
申请日：2018-06-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwan Ho Kim , Dohan Kim , Jinmin Bang
Abstract: An electronic device according to various embodiments of the present invention may comprise: a processor; and an image sensor module electrically connected to the processor, wherein the image sensor module comprises: an image sensor; and a control circuit electrically connected to the image sensor and connected to the processor via an interface, and the control circuit is configured to: receive a signal for capturing an image of an external object; acquire multiple pieces of raw image data of the external object, using the image sensor; generate pixel information data associated with control of the image capture by the processor, using at least a part of the acquired multiple pieces of raw image data; generate compressed data obtained by compressing at least a part of the multiple pieces of raw image data; transmit the pixel information data to the processor according to a transmission period designated by the processor or the control circuit; and transmit the compressed data to the processor.
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