公开(公告)号：US20240133683A1

公开(公告)日：2024-04-25

申请号：US18460929

申请日：2023-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inho KWAK ,  Jinsun KIM ,  Moosong LEE ,  Seungyoon LEE ,  Jeongjin LEE ,  Chan HWANG ,  Dohyeon PARK ,  Yeeun HAN

IPC: G01B15/00

CPC classification number: G01B15/00

Abstract: In an overlay measurement method, an overlay mark having programmed overlay values is provided. The overlay mark is scanned with an electron beam to obtain a voltage contrast image. A defect function that changes according to the overlay value is obtained from voltage contrast image data. Self-cross correlation is performed on the defect function to determine an overlay.

公开(公告)号：US20240220103A1

公开(公告)日：2024-07-04

申请号：US18231829

申请日：2023-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dohyeon PARK ,  Dongeun SHIN ,  Jinhyuk LEE

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0688

Abstract: A method of operating a storage device including a plurality of nonvolatile memory devices and a storage controller, including: generating a parity chunk by performing a redundant array of independent disks (RAID) encoding on a plurality of data chunks; storing a data stripe including the plurality of data chunks and the parity chunk in a plurality of memory blocks included in the plurality of nonvolatile memory devices; and performing a direct read operation or an indirect read operation based on an operating state of the storage device such that in the direct read operation a target data chunk is directly read from the plurality of nonvolatile memory devices, and in the indirect read operation the target data chunk is generated by performing a RAID decoding.

公开(公告)号：US20230411393A1

公开(公告)日：2023-12-21

申请号：US18140789

申请日：2023-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moosong LEE ,  Jinsun KIM ,  Inho KWAK ,  Dohyeon PARK ,  Yeeun HAN ,  Sang-Ho YUN ,  Seungyoon LEE ,  Nanhyung KIM

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L27/0924 ,  H01L29/66545 ,  H01L27/0207 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a key region, a dummy active pattern on the key region, the dummy active pattern including a first impurity region and a second impurity region, a line structure provided on the first impurity region and extended in a first direction, a dummy gate electrode provided between the first and second impurity regions and extended in a second direction crossing the first direction, and a dummy contact disposed adjacent to a side of the line structure and connected to the second impurity region. The dummy contact includes a plurality of long contacts arranged in the second direction.