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公开(公告)号:US20190333935A1
公开(公告)日:2019-10-31
申请号:US16506609
申请日:2019-07-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seok Cheon BAEK , Young Woo Kim , Dong Sik Lee , Min Yong Lee , Woong Seop Lee
IPC: H01L27/11582 , H01L27/11573 , H01L27/11575 , H01L27/1157 , H01L27/11565 , H01L27/11556 , H01L23/522 , H01L27/11521 , H01L27/11526 , H01L29/06 , H01L27/11568 , H01L23/528
Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.
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公开(公告)号:US20200227435A1
公开(公告)日:2020-07-16
申请号:US16686967
申请日:2019-11-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sung Min Hwang , Joon Sung Lim , Woo Sung Yang , Dong Sik Lee
IPC: H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/11529 , H01L27/1157 , H01L27/11573
Abstract: A semiconductor device includes gate electrodes spaced apart from each other in a first direction perpendicular to a substrate's upper surface, and extending by different lengths in a second direction perpendicular to the first direction. The device further includes first and second channels penetrating the gate electrodes and extending in the first direction, a horizontal portion disposed in lower portions of the gate electrodes and connecting lower portions of the first and second channels to each other, and a source line disposed in an upper portion of the second channel and connected to the second channel. The gate electrodes include memory cell electrodes included in memory cells, a first ground select electrode disposed in lower portions of the memory cell electrodes, a second ground select electrode disposed in upper portions of the memory cell electrodes, and a string select electrode disposed in upper portions of the memory cell electrodes.
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公开(公告)号:US11139314B2
公开(公告)日:2021-10-05
申请号:US16686967
申请日:2019-11-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sung Min Hwang , Joon Sung Lim , Woo Sung Yang , Dong Sik Lee
IPC: H01L27/11582 , H01L27/1157 , H01L27/11573
Abstract: A semiconductor device includes gate electrodes spaced apart from each other in a first direction perpendicular to a substrate's upper surface, and extending by different lengths in a second direction perpendicular to the first direction. The device further includes first and second channels penetrating the gate electrodes and extending in the first direction, a horizontal portion disposed in lower portions of the gate electrodes and connecting lower portions of the first and second channels to each other, and a source line disposed in an upper portion of the second channel and connected to the second channel. The gate electrodes include memory cell electrodes included in memory cells, a first ground select electrode disposed in lower portions of the memory cell electrodes, a second ground select electrode disposed in upper portions of the memory cell electrodes, and a string select electrode disposed in upper portions of the memory cell electrodes.
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公开(公告)号:US10373975B2
公开(公告)日:2019-08-06
申请号:US16162720
申请日:2018-10-17
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seok Cheon Baek , Young Woo Kim , Dong Sik Lee , Min Yong Lee , Woong Seop Lee
IPC: H01L27/11582 , H01L23/522 , H01L23/528 , H01L27/11521 , H01L27/11526 , H01L27/11556 , H01L27/11568 , H01L27/11573 , H01L29/06 , H01L27/11565 , H01L27/1157 , H01L27/11575
Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.
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公开(公告)号:US10128263B2
公开(公告)日:2018-11-13
申请号:US15224238
申请日:2016-07-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seok Cheon Baek , Young Woo Kim , Dong Sik Lee , Min Yong Lee , Woong Seop Lee
IPC: H01L29/76 , H01L27/11582 , H01L23/522 , H01L23/528 , H01L27/11521 , H01L27/11526 , H01L27/11556 , H01L27/11568 , H01L27/11573 , H01L29/06
Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.
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