公开(公告)号：US10373975B2

公开(公告)日：2019-08-06

申请号：US16162720

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek ,  Young Woo Kim ,  Dong Sik Lee ,  Min Yong Lee ,  Woong Seop Lee

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/06 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.

公开(公告)号：US10128263B2

公开(公告)日：2018-11-13

申请号：US15224238

申请日：2016-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek ,  Young Woo Kim ,  Dong Sik Lee ,  Min Yong Lee ,  Woong Seop Lee

IPC: H01L29/76 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/06

Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.

公开(公告)号：US20250071992A1

公开(公告)日：2025-02-27

申请号：US18604586

申请日：2024-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Yong Lee ,  Se Hoon Lee ,  Jun Hyoung Kim ,  Ji Young Kim ,  Suk Kang Sung

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor memory device may include a cell substrate including a first surface and a second surface opposite to the first surface, and a landing pattern including a third surface and a fourth surface opposite to the third surface, with the landing pattern spaced apart from the cell substrate in a horizontal direction. The semiconductor memory device may include a plurality of gate electrodes sequentially stacked on the first surface and the third surface, a channel structure on the cell substrate, the channel structure extending vertically and intersecting the plurality of gate electrodes, an upper insulating film covering the second surface and the fourth surface, an input/output pad on the upper insulating film, the input/output pad overlapping at least a portion of the plurality of gate electrodes in the vertical direction, and a support contact extending through the upper insulating film and connecting the landing pattern and the input/output pad.

公开(公告)号：US20190333935A1

公开(公告)日：2019-10-31

申请号：US16506609

申请日：2019-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Cheon BAEK ,  Young Woo Kim ,  Dong Sik Lee ,  Min Yong Lee ,  Woong Seop Lee

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/06 ,  H01L27/11568 ,  H01L23/528

Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.