公开(公告)号：US20190333935A1

公开(公告)日：2019-10-31

申请号：US16506609

申请日：2019-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Cheon BAEK ,  Young Woo Kim ,  Dong Sik Lee ,  Min Yong Lee ,  Woong Seop Lee

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/06 ,  H01L27/11568 ,  H01L23/528

Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.

公开(公告)号：US20170186767A1

公开(公告)日：2017-06-29

申请号：US15224238

申请日：2016-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon BAEK ,  YOUNG WOO KIM ,  DONG SIK LEE ,  MIN YONG LEE ,  WOONG SEOP LEE

IPC: H01L27/115 ,  H01L23/522 ,  H01L29/06 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0649

Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.

公开(公告)号：US20210193681A1

公开(公告)日：2021-06-24

申请号：US17196005

申请日：2021-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon BAEK

IPC: H01L27/11582 ,  H01L21/02 ,  H01L21/768 ,  H01L29/10 ,  H01L23/48 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573

Abstract: A vertical memory device includes a substrate having a peripheral circuit interconnection, lower word lines stacked on the substrate, vertical channel structures passing through the lower word lines, a first cell contact plug including a bottom end lower than a bottom surface of a first lower word line and being connected to the first lower word line, and lower insulating layers and first lower mold patterns positioned beneath the first lower word line and stacked alternately on each other from the substrate.

公开(公告)号：US20190237477A1

公开(公告)日：2019-08-01

申请号：US16162533

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon BAEK ,  Sung Hun LEE

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  G11C7/18 ,  G11C8/14 ,  H01L29/423

CPC classification number: H01L27/11582 ,  G11C7/18 ,  G11C8/14 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/4234

Abstract: A three-dimensional semiconductor memory device including a gate-stack structure on a base substrate, the gate-stack structure including gate electrodes stacked in a direction perpendicular to a surface of the base substrate and spaced apart from each other; a through region penetrating through the gate-stack structure and surrounded by the gate-stack structure; and first vertical channel structures and second vertical channel structures on both sides of the through region and penetrating through the gate-stack structure, wherein the through region is between the first vertical channel structures and the second vertical channel structures.

公开(公告)号：US20220278125A1

公开(公告)日：2022-09-01

申请号：US17747174

申请日：2022-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Seon AHN ,  Ji Sung CHEON ,  Young Jin KWON ,  Seok Cheon BAEK ,  Woong Seop LEE

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/11573 ,  H01L21/28 ,  H01L27/11565

Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.

公开(公告)号：US20200091170A1

公开(公告)日：2020-03-19

申请号：US16174187

申请日：2018-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon BAEK

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/528 ,  H01L29/10 ,  H01L23/48 ,  H01L21/768 ,  H01L21/02 ,  H01L27/11565 ,  H01L27/11568

Abstract: A vertical memory device includes a substrate having a peripheral circuit interconnection, lower word lines stacked on the substrate, vertical channel structures passing through the lower word lines, a first cell contact plug including a bottom end lower than a bottom surface of a first lower word line and being connected to the first lower word line, and lower insulating layers and first lower mold patterns positioned beneath the first lower word line and stacked alternately on each other from the substrate.

公开(公告)号：US20190378852A1

公开(公告)日：2019-12-12

申请号：US16206035

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon BAEK ,  Geun Won LIM

IPC: H01L27/11575 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/535 ,  H01L21/28 ,  H01L21/768

Abstract: A method for fabricating a non-volatile memory device is provided. The method includes forming a channel hole and a first contact hole simultaneously, several times, in order to achieve a desired a high aspect ratio.

公开(公告)号：US20230189524A1

公开(公告)日：2023-06-15

申请号：US17884853

申请日：2022-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Gu KANG ,  Sang Don ZOO ,  Joon Sung KIM ,  Junghwan PARK ,  Seorim MOON ,  Seok Cheon BAEK ,  Cheol RYOU ,  Sun Young LEE ,  Cheol-Min LIM

IPC: H01L27/11582 ,  H01L23/535

CPC classification number: H01L27/11582 ,  H01L23/535

Abstract: A semiconductor memory device may include a substrate including a first and a second block region, and a stacked structure including insulating films and gate electrodes alternately stacked on the substrate. A vertical channel structure, a word line cut structure, and a block cut structure may penetrate the stacked structure. The word line cut structure may extend in a second direction. The block cut structure may extend in a first direction, connect to the word line cut structure, and define the first and second block regions. The block cut structure may include a first portion connected to the word line cut structure and a second portion connected to the first portion. From a planar viewpoint, the first portion may include at least a part not overlapping the second portion in the first direction and at least a region not overlapping the word line cut structure in the first direction.

公开(公告)号：US20200266212A1

公开(公告)日：2020-08-20

申请号：US16869581

申请日：2020-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon BAEK

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/528 ,  H01L29/10 ,  H01L23/48 ,  H01L27/11568 ,  H01L21/768 ,  H01L21/02 ,  H01L27/11565

Abstract: A vertical memory device includes a substrate having a peripheral circuit interconnection, lower word lines stacked on the substrate, vertical channel structures passing through the lower word lines, a first cell contact plug including a bottom end lower than a bottom surface of a first lower word line and being connected to the first lower word line, and lower insulating layers and first lower mold patterns positioned beneath the first lower word line and stacked alternately on each other from the substrate.

公开(公告)号：US20200058671A1

公开(公告)日：2020-02-20

申请号：US16270570

申请日：2019-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hyoung KIM ,  Kwang Soo KIM ,  Seok Cheon BAEK ,  Geun Won LIM

IPC: H01L27/11575 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.