公开(公告)号：US20220359507A1

公开(公告)日：2022-11-10

申请号：US17871077

申请日：2022-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongchan SUH ,  Dahye KIM

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78

Abstract: Provided is an integrated circuit device including: a plurality of fin-type active regions protruding from a top surface of a substrate and extending in a first horizontal direction; at least one semiconductor layer, each including a lower semiconductor layer and an upper semiconductor layer sequentially stacked on at least one of the plurality of fin-type active regions; and a plurality of gate electrodes extending in a second horizontal direction crossing the first horizontal direction on the plurality of fin-type active regions, wherein the lower semiconductor layer includes a same material as a material of the upper semiconductor layer, and wherein a semiconductor interface is provided between the lower semiconductor layer and the upper semiconductor layer.

公开(公告)号：US20200381427A1

公开(公告)日：2020-12-03

申请号：US16704448

申请日：2019-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongchan SUH ,  Dahye KIM

IPC: H01L27/088 ,  H01L21/8234

Abstract: Provided is an integrated circuit device including: a plurality of fin-type active regions protruding from a top surface of a substrate and extending in a first horizontal direction; at least one semiconductor layer, each including a lower semiconductor layer and an upper semiconductor layer sequentially stacked on at least one of the plurality of fin-type active regions; and a plurality of gate electrodes extending in a second horizontal direction crossing the first horizontal direction on the plurality of fin-type active regions, wherein the lower semiconductor layer includes a same material as a material of the upper semiconductor layer, and wherein a semiconductor interface is provided between the lower semiconductor layer and the upper semiconductor layer.

公开(公告)号：US20220149040A1

公开(公告)日：2022-05-12

申请号：US17584877

申请日：2022-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungryul LEE ,  Yongseung KIM ,  Jungtaek KIM ,  Pankwi PARK ,  Dongchan SUH ,  Moonseung YANG ,  Seojin JEONG ,  Minhee CHOI ,  Ryong HA

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.

公开(公告)号：US20210367083A1

公开(公告)日：2021-11-25

申请号：US17396059

申请日：2021-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dahye KIM ,  Dongchan SUH ,  Jinbum KIM

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes an active region extending on a substrate in a first direction and including an impurity region, a plurality of channel layers vertically spaced apart from each other on the active region, a gate structure extending on the substrate in a second direction to intersect the active region and the plurality of channel layers, and surrounding the plurality of channel layers, a source/drain region disposed on the active region on at least one side of the gate structure and in contact with the plurality of channel layers, a barrier layer including a first barrier layer spaced apart from an upper surface of the active region and being disposed in the active region, and second barrier layers respectively disposed below the plurality of channel layers, and a contact plug connected to the source/drain region.

公开(公告)号：US20230007959A1

公开(公告)日：2023-01-12

申请号：US17804102

申请日：2022-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyeong JOE ,  Dongchan SUH ,  Sungkeun LIM ,  Seokhoon KIM ,  Pankwi PARK ,  Dongsuk SHIN

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a first active region, a second active region spaced apart from the first active region, a plurality of first channel layers disposed on the first active region, and a second channel layer disposed on the second active region. The semiconductor device further includes a first gate structure intersecting the first active region and the first channel layers, a second gate structure intersecting the second active region and the second channel layer, a first source/drain region disposed on the first active region and contacting the plurality of first channel layers, and a second source/drain region and contacting the second channel layer. The plurality of first channel layers includes a first uppermost channel layer and first lower channel layers disposed below the first uppermost channel layer, and the first uppermost channel layer includes a material that is different from a material included in the first lower channel layers.

公开(公告)号：US20210082914A1

公开(公告)日：2021-03-18

申请号：US16841806

申请日：2020-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungryul LEE ,  Yongseung KIM ,  Jungtaek KIM ,  Pankwi PARK ,  Dongchan SUH ,  Moonseung YANG ,  Seojin JEONG ,  Minhee CHOI ,  Ryong HA

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

Abstract: An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.