公开(公告)号：US20230223405A1

公开(公告)日：2023-07-13

申请号：US18122253

申请日：2023-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee CHOI ,  Keunhwi CHO ,  Myunggil KANG ,  Seokhoon KIM ,  Dongwon KIM ,  Pankwi PARK ,  Dongsuk SHIN

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/167 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/66439

Abstract: An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.

公开(公告)号：US20220149040A1

公开(公告)日：2022-05-12

申请号：US17584877

申请日：2022-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungryul LEE ,  Yongseung KIM ,  Jungtaek KIM ,  Pankwi PARK ,  Dongchan SUH ,  Moonseung YANG ,  Seojin JEONG ,  Minhee CHOI ,  Ryong HA

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.

公开(公告)号：US20230207626A1

公开(公告)日：2023-06-29

申请号：US17874945

申请日：2022-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namkyu CHO ,  Sanggil LEE ,  Seokhoon KIM ,  Pankwi PARK

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/40

CPC classification number: H01L29/0847 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41775 ,  H01L29/78684 ,  H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/401 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate including center and edge regions, active patterns on the substrate, channel patterns on the active patterns, source/drain patterns connected to the channel patterns, and gate electrodes on the channel patterns. Each of the source/drain patterns may include a buffer layer in contact with a corresponding one of the channel patterns and a main layer on the buffer layer. The main layer of each of the source/drain patterns may include first and second semiconductor layers, which may be sequentially stacked and contain germanium. A concentration of the germanium in the first semiconductor layer may be higher on the center region than on the edge region, and a concentration of the germanium in the second semiconductor layer may be lower on the center region than on the edge region.

公开(公告)号：US20230326985A1

公开(公告)日：2023-10-12

申请号：US18201308

申请日：2023-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ryong HA ,  Dongwoo KIM ,  Gyeom KIM ,  Yong Seung KIM ,  Pankwi PARK ,  Seung Hun LEE

IPC: H01L29/423 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/41758 ,  H01L29/1033 ,  H01L29/42356

Abstract: A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.

公开(公告)号：US20230326970A1

公开(公告)日：2023-10-12

申请号：US18050684

申请日：2022-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namkyu CHO ,  Seokhoon KIM ,  Jeongho YOO ,  Choeun LEE ,  Pankwi PARK ,  Dongsuk SHIN

IPC: H01L29/08 ,  H01L29/786 ,  H01L27/092 ,  H01L29/66 ,  H01L29/775 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417 ,  H01L21/8238

CPC classification number: H01L29/0847 ,  H01L29/78696 ,  H01L27/092 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/41783 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/0673

Abstract: A semiconductor device includes a substrate including a first active pattern, a first channel pattern on the first active pattern, the first channel pattern including first, second, and third semiconductor patterns spaced apart from one another and vertically stacked, a first source/drain pattern connected to the first to third semiconductor patterns, and a gate electrode on the first to third semiconductor patterns. The first source/drain pattern includes a first protrusion protruding toward the first semiconductor pattern, a second protrusion protruding toward the second semiconductor pattern, and a third protrusion protruding toward the third semiconductor pattern. A width of the second protrusion is greater than a width of the first protrusion. A width of the third protrusion is greater than the width of the second protrusion.

公开(公告)号：US20240243188A1

公开(公告)日：2024-07-18

申请号：US18513759

申请日：2023-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyohoon BYEON ,  Seokhoon KIM ,  Unki KIM ,  Pankwi PARK ,  Sungkeun LIM ,  Yuyeong JO

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes: a rear wiring structure; an insulating substrate including fin structures disposed on the rear wiring structure and extending in a first horizontal direction; a device isolation layer disposed between the fin structures; a lower insulating layer covering the fin structures; gate structures extending in a second horizontal direction crossing the first horizontal direction; a plurality of nanosheet stacks disposed on the lower insulating layer; a first source/drain region disposed on the insulating substrate and including a body portion and a vertical extension portion, wherein the body portion is disposed between the plurality of nanosheet stacks, and the vertical extension portion passes through the lower insulating layer and through some of the fin structures; a semiconductor epitaxial structure at least partially surrounding the vertical extension portion of the first source/drain region; and a lower contact connecting the semiconductor epitaxial structure with the rear wiring structure.

公开(公告)号：US20240153954A1

公开(公告)日：2024-05-09

申请号：US18414039

申请日：2024-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee CHOI ,  Keunhwi CHO ,  Myunggil KANG ,  Seokhoon KIM ,  Dongwon KIM ,  Pankwi PARK ,  Dongsuk SHIN

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851

Abstract: An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.

公开(公告)号：US20230395661A1

公开(公告)日：2023-12-07

申请号：US18149957

申请日：2023-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sumin YU ,  Jungtaek KIM ,  Moonseung YANG ,  Seojin JEONG ,  Edward CHO ,  Seokhoon KIM ,  Pankwi PARK

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/775 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/66439 ,  H01L29/775 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545 ,  H01L29/42392

Abstract: An integrated circuit (IC) device including fin-type active regions parallel to each other on a substrate, the fin-type active regions extending in a first lateral direction, a first nanosheet stack apart from a fin top surface of a first fin-type active region selected from the fin-type active regions, the first nanosheet stack including at least one nanosheet facing the fin top surface of the first fin-type active region, a gate structure surrounding the first nanosheet stack, the gate structure extending in a second lateral direction, a first source/drain region in contact with one sidewall of the first nanosheet stack, and a second source/drain region in contact with another sidewall of the first nanosheet stack , wherein a greatest width of the first source/drain region is less than a greatest width of the second source/drain region in the second lateral direction may be provided.

公开(公告)号：US20230007959A1

公开(公告)日：2023-01-12

申请号：US17804102

申请日：2022-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyeong JOE ,  Dongchan SUH ,  Sungkeun LIM ,  Seokhoon KIM ,  Pankwi PARK ,  Dongsuk SHIN

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a first active region, a second active region spaced apart from the first active region, a plurality of first channel layers disposed on the first active region, and a second channel layer disposed on the second active region. The semiconductor device further includes a first gate structure intersecting the first active region and the first channel layers, a second gate structure intersecting the second active region and the second channel layer, a first source/drain region disposed on the first active region and contacting the plurality of first channel layers, and a second source/drain region and contacting the second channel layer. The plurality of first channel layers includes a first uppermost channel layer and first lower channel layers disposed below the first uppermost channel layer, and the first uppermost channel layer includes a material that is different from a material included in the first lower channel layers.

公开(公告)号：US20210217860A1

公开(公告)日：2021-07-15

申请号：US17141513

申请日：2021-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ryong HA ,  Dongwoo KIM ,  Gyeom KIM ,  Yong Seung KIM ,  Pankwi PARK ,  Seung Hun LEE

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.