公开(公告)号：US20240405113A1

公开(公告)日：2024-12-05

申请号：US18537916

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yang XU ,  Gyeom KIM ,  Young Kwang KIM ,  Jin Bum KIM ,  Yoon Tae NAM ,  Kyung Bin CHUN ,  Ryong HA ,  Yoon HEO

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate. An active pattern extends in a first horizontal direction on the substrate. First to third nanosheets are sequentially spaced apart from each other in a vertical direction on the active pattern. A gate electrode extends in a second horizontal direction on the active pattern and surrounds the first to third nanosheets. A source/drain region includes a first layer disposed along side walls and a bottom surface of a source/drain trench and a second layer filling the source/drain trench. The second layer includes a first lower side wall facing a side wall of the first nanosheet and an opposite second lower side wall. A lower surface connects the first and second lower side walls and extends in the first horizontal direction. The first and second lower side walls of the second layer extend to have a constant slope in opposite directions to each other.

公开(公告)号：US20240297234A1

公开(公告)日：2024-09-05

申请号：US18661171

申请日：2024-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seo Jin JEONG ,  Do Hyun GO ,  Seok Hoon KIM ,  Jung Taek KIM ,  Pan Kwi PARK ,  Moon Seung YANG ,  Min-Hee CHOI ,  Ryong HA

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.

公开(公告)号：US20230326985A1

公开(公告)日：2023-10-12

申请号：US18201308

申请日：2023-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ryong HA ,  Dongwoo KIM ,  Gyeom KIM ,  Yong Seung KIM ,  Pankwi PARK ,  Seung Hun LEE

IPC: H01L29/423 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/41758 ,  H01L29/1033 ,  H01L29/42356

Abstract: A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.

公开(公告)号：US20220181498A1

公开(公告)日：2022-06-09

申请号：US17391342

申请日：2021-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Taek KIM ,  Seok Hoon KIM ,  Ryong HA ,  Pan Kwi PARK ,  Dong Suk SHIN

IPC: H01L29/786 ,  H01L29/66

Abstract: There is provided a semiconductor device comprising an active pattern, including a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction perpendicular to the first direction, a plurality of gate structures on the lower pattern to be spaced apart from each other in the first direction and including a gate electrode and a gate insulating film wrapping the plurality of sheet patterns, a source/drain recess defined between the gate structures adjacent to each other, and a source/drain pattern inside the source/drain recess and including a semiconductor blocking film formed continuously along the source/drain recess, wherein the source/drain recesses include a plurality of width extension regions, and a width of each of the width extension regions in the first direction increases and then decreases, as it goes away from an upper surface of the lower pattern.

公开(公告)号：US20220149040A1

公开(公告)日：2022-05-12

申请号：US17584877

申请日：2022-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungryul LEE ,  Yongseung KIM ,  Jungtaek KIM ,  Pankwi PARK ,  Dongchan SUH ,  Moonseung YANG ,  Seojin JEONG ,  Minhee CHOI ,  Ryong HA

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.

公开(公告)号：US20180342583A1

公开(公告)日：2018-11-29

申请号：US15800483

申请日：2017-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Kwan YU ,  Hyo Jin KIM ,  Ryong HA

IPC: H01L29/08 ,  H01L27/092 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/76224 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/7848 ,  H01L29/7854

Abstract: A semiconductor device is provided. The semiconductor device includes a fin-type pattern formed on a substrate and including first and second sidewalls, which are defined by a trench, a field insulating film placed in contact with the first and second sidewalls and filling the trench, and an epitaxial pattern formed on the fin-type pattern and including a first epitaxial layer and a second epitaxial layer, which is formed on the first epitaxial layer.

公开(公告)号：US20220190134A1

公开(公告)日：2022-06-16

申请号：US17460446

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEO JIN JEONG ,  Do Hyun GO ,  Seok Hoon KIM ,  Jung Taek KIM ,  Pan Kwi PARK ,  Moon Seung YANG ,  Min-Hee CHOI ,  Ryong HA

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417

Abstract: A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.

公开(公告)号：US20210217860A1

公开(公告)日：2021-07-15

申请号：US17141513

申请日：2021-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ryong HA ,  Dongwoo KIM ,  Gyeom KIM ,  Yong Seung KIM ,  Pankwi PARK ,  Seung Hun LEE

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.

公开(公告)号：US20210082914A1

公开(公告)日：2021-03-18

申请号：US16841806

申请日：2020-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungryul LEE ,  Yongseung KIM ,  Jungtaek KIM ,  Pankwi PARK ,  Dongchan SUH ,  Moonseung YANG ,  Seojin JEONG ,  Minhee CHOI ,  Ryong HA

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

Abstract: An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.