公开(公告)号：US20210225868A1

公开(公告)日：2021-07-22

申请号：US17009075

申请日：2020-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungeun PARK ,  Jae-Joo SHIM ,  Dongsung WOO ,  Jongkwang LIM ,  Jaehoon JANG

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11539 ,  G11C7/18

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising a substrate including a cell region and a connection region, a plurality of inter-electrode dielectric layers and a plurality of electrode layers alternately stacked on the substrate, wherein ends of the plurality of electrode layers form a stepwise shape on the connection region, a planarized dielectric layer on the connection region and covering the ends of the plurality of electrode layers, and a first abnormal dummy vertical pattern on the connection region and penetrating the planarized dielectric layer in a first direction perpendicular to a top surface of the substrate. At least one of the plurality of electrode layers is positioned between the first abnormal dummy vertical pattern and the substrate and is insulated from the first abnormal dummy vertical pattern.

公开(公告)号：US20230094302A1

公开(公告)日：2023-03-30

申请号：US17747412

申请日：2022-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Dongsung WOO ,  Tae Gon LEE ,  Bongtae PARK ,  Jae-Joo SHIM ,  Tae-Chul JUNG

IPC: H01L27/11526 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573

Abstract: A semiconductor device and an electronic system including the same are disclosed. The semiconductor device may include a substrate including a cell array region and a connection region, the cell array region comprising a center region and an outer region; an electrode structure including electrodes and pads; vertical structures on the cell array region and penetrating the electrode structure; and a separation insulating pattern penetrating and dividing an upper electrode, which is one of the electrodes, into at least two portions arranged in a second direction crossing the first direction. The separation insulating pattern comprises a first portion and a second portion, the first portion is between at least some of the central vertical structures, and the second portion is spaced apart from the first portion such that, when viewed in the plan view, the second portion is between at least some of the peripheral vertical structure.

公开(公告)号：US20230026774A1

公开(公告)日：2023-01-26

申请号：US17709803

申请日：2022-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin HWANG ,  Taewon KANG ,  Dongsung WOO ,  Taegon LEE ,  Bongtae PARK ,  Jaejoo SHIM

IPC: H01L27/108

Abstract: A semiconductor device and a data storage system including the same, the semiconductor device including a substrate structure; a stack structure; a vertical memory structure; a vertical dummy structure; and an upper separation pattern, wherein hen viewed on a plane at a first height level, higher than a height level of a lowermost end of the upper separation pattern, the dummy channel layer includes a first dummy channel region facing the dummy data storage layer and a second dummy channel region facing the dummy data storage layer, the first dummy channel region having a thickness different from a thickness of the second dummy channel region.