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    NONVOLATILE MEMORY DEVICES AND OPERATING METHODS THEREOF
    1.
    发明申请
    NONVOLATILE MEMORY DEVICES AND OPERATING METHODS THEREOF 有权
    非易失性存储器件及其操作方法

    公开(公告)号：US20130107629A1

    公开(公告)日：2013-05-02

    申请号：US13721963

    申请日：2012-12-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunil SHIM ,  Jaehoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

    IPC: G11C16/30 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3459 ,  H01L27/1157 ,  H01L27/11582

    Abstract: According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array including a plurality of memory cells; a word line driver configured to at least one of select and unselect a plurality of word lines connected with the plurality of memory cells, respectively, and to supply voltages to the plurality of word lines; and a read/write circuit configured to apply bias voltages to a plurality of bit lines connected with the plurality of memory cells. The read/write circuit may be configured to adjust levels of the bias voltages applied to the plurality of bit lines according to location of a selected word line among the plurality of word lines.

    Abstract translation: 根据发明构思的示例实施例，非易失性存储器件包括包括多个存储器单元的存储单元阵列; 字线驱动器，被配置为分别选择和取消选择与所述多个存储器单元连接的多个字线中的至少一个，并向所述多个字线提供电压; 以及读/写电路，被配置为向与多个存储单元连接的多个位线施加偏置电压。 读/写电路可以被配置为根据多个字线中所选择的字线的位置来调整施加到多个位线的偏置电压的电平。

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开
    三维半导体存储器件

    公开(公告)号：US20150357339A1

    公开(公告)日：2015-12-10

    申请号：US14826814

    申请日：2015-08-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunil SHIM ,  Jang-Gn YUN ,  Jeonghyuk CHOI ,  Kwang Soo SEOL ,  Jaehoon JANG ,  Jungdal CHOI

    IPC: H01L27/115 ,  H01L23/535

    CPC classification number: G11C16/0466 ,  G11C16/0483 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.

    Abstract translation: 提供一种半导体存储器件，包括形成在衬底上的第一和第二单元串，第一和第二单元串共同连接到位线，其中第一和第二单元串中的每一个包括地选择单元，存储单元和 第一和第二串选择单元，其顺序地形成在要连接的基板上，其中，所述接地选择单元连接到地选择线，所述存储单元连接到字线，所述第一串选择单元连接到 第一串选择线，第二串选择单元连接到第二串选择线，并且其中第一单元串的第二串选择单元具有沟道掺杂区。

    HINGE ASSEMBLY AND ELECTRONIC DEVICE INCLUDING THE SAME
    4.
    发明申请
    HINGE ASSEMBLY AND ELECTRONIC DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20230053373A1

    公开(公告)日：2023-02-23

    申请号：US17897329

    申请日：2022-08-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jongkeun KIM ,  Yonghwa HAN ,  Myungchul RYU ,  Sukjin YUN ,  Jaehoon JANG

    IPC: H04M1/02 ,  F16C11/04

    Abstract: An electronic device includes a display, and a hinge assembly foldable together with the display and corresponding to a folding area of the display. The hinge assembly includes a hinge bracket defining first and second hinge axes, first and second rotators connected to the hinge bracket and respectively rotatable about the first and second hinge axes, first and second sliders connected to the hinge bracket, respectively slidable relative to the hinge bracket in a direction parallel with the hinge axes, and spaced apart from each other in the direction, and an elastic member between the first and second sliders and providing an elastic force in the direction. The first and second rotators respectively include first and second helical structures having a helical shape with the first and second hinge axes as a center, and are each connected to the first and second sliders through the first and second helical structures.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210225868A1

    公开(公告)日：2021-07-22

    申请号：US17009075

    申请日：2020-09-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungeun PARK ,  Jae-Joo SHIM ,  Dongsung WOO ,  Jongkwang LIM ,  Jaehoon JANG

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11539 ,  G11C7/18

    Abstract: Disclosed is a three-dimensional semiconductor memory device comprising a substrate including a cell region and a connection region, a plurality of inter-electrode dielectric layers and a plurality of electrode layers alternately stacked on the substrate, wherein ends of the plurality of electrode layers form a stepwise shape on the connection region, a planarized dielectric layer on the connection region and covering the ends of the plurality of electrode layers, and a first abnormal dummy vertical pattern on the connection region and penetrating the planarized dielectric layer in a first direction perpendicular to a top surface of the substrate. At least one of the plurality of electrode layers is positioned between the first abnormal dummy vertical pattern and the substrate and is insulated from the first abnormal dummy vertical pattern.

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