公开(公告)号：US20230352068A1

公开(公告)日：2023-11-02

申请号：US18124094

申请日：2023-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Duhwi Kim ,  Junghak Song ,  Chanho Lee

IPC: G11C7/10 ,  G11C8/08

CPC classification number: G11C7/1096 ,  G11C7/1087 ,  G11C7/1069 ,  G11C8/08

Abstract: A memory device includes a plurality of multi-bit cells, wherein each of the plurality of multi-bit cells includes a plurality of bit cells commonly connected to a column selection line, respectively connected to a plurality of write word lines, and respectively connected to a plurality of read word lines and an input circuit configured to provide a first signal corresponding to a bit to be written, to the plurality of bit cells, wherein each of the plurality of bit cells includes a latch circuit configured to receive the first signal in response to a write word line being activated and latch the first signal in response to the write word line being deactivated or a column selection line being deactivated, and a read circuit configured to output the first signal stored in the latch circuit to a bit line in response to a read word line being activated.

公开(公告)号：US20240412771A1

公开(公告)日：2024-12-12

申请号：US18507444

申请日：2023-11-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiryong Kim ,  Jungmyung Kang ,  Inhak Lee ,  Jaesung Choi ,  Jeonseung Kang ,  Duhwi Kim ,  Jaeyoung Kim

IPC: G11C11/4074 ,  G11C11/4072 ,  G11C11/4096

Abstract: An embedded memory device includes a retention voltage supply circuit outputting a retention voltage in response to a retention activation signal, and a plurality of array voltage supply circuits outputting corresponding array voltages to corresponding bit cells. The plurality of array voltage supply circuits respectively include an array switch providing the retention voltage as a corresponding array voltage in response to the retention activation signal, a power switch providing a power supply voltage as the corresponding array voltage in response to a power gate activation signal, and an auxiliary circuit compensating the corresponding array voltage during a write operation or a read operation.