公开(公告)号：US10699915B2

公开(公告)日：2020-06-30

申请号：US16234815

申请日：2018-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Lee ,  Hyunsoo Chung ,  Hansung Ryu ,  Inyoung Lee

IPC: H01L21/50 ,  H01L23/48 ,  H01L23/00 ,  H01L23/58 ,  H01L23/373 ,  H01L21/48 ,  H01L21/02 ,  H01L23/544 ,  H01L25/065 ,  H01L21/768 ,  H01L23/31

Abstract: A semiconductor device including a substrate, an insulating layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

公开(公告)号：US11574819B2

公开(公告)日：2023-02-07

申请号：US17188404

申请日：2021-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Lee ,  Hyunsoo Chung ,  Hansung Ryu ,  InYoung Lee

IPC: H01L21/50 ,  H01L23/48 ,  H01L23/00 ,  H01L23/58 ,  H01L23/373 ,  H01L21/48 ,  H01L21/02 ,  H01L23/544 ,  H01L25/065 ,  H01L21/768 ,  H01L23/31

Abstract: A semiconductor device including a substrate, an insulating layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

公开(公告)号：US20170084559A1

公开(公告)日：2017-03-23

申请号：US15230889

申请日：2016-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong Soon Park ,  Hyunsoo Chung ,  Won-young Kim ,  Ae-nee Jang ,  Chanho Lee

IPC: H01L23/00

CPC classification number: H01L23/50 ,  H01L24/02 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06139 ,  H01L2224/06151 ,  H01L2224/06152 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/06159 ,  H01L2224/0616 ,  H01L2224/06165 ,  H01L2224/06169 ,  H01L2224/06177 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/0613

Abstract: Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.

公开(公告)号：US20240332431A1

公开(公告)日：2024-10-03

申请号：US18497363

申请日：2023-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin Seo ,  Sukkang Sung ,  Cheonan Lee ,  Sangeun Lee ,  Chanho Lee

IPC: H01L29/861 ,  H01L27/02

CPC classification number: H01L29/8611 ,  H01L27/0248

Abstract: A semiconductor device according to an embodiment of the present inventive concept comprises: a first power supply pad configured to receive a first power supply voltage; a second power supply pad configured to receive a second power supply voltage, the second power supply voltage having a level lower than a level of the first power supply voltage; a signal pad configured to exchange a signal; and a first electrostatic discharge (ESD) diode comprising a first impurity region doped with impurities of a first conductivity type and connected to the first power supply pad, and a second impurity region doped with impurities of a second conductivity type different from the first conductivity type and connected to the signal pad, wherein a lower surface of at least one of the first impurity region and the second impurity region has an uneven structure.

公开(公告)号：US11705379B2

公开(公告)日：2023-07-18

申请号：US17087879

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Lee ,  Won Kim ,  Haeseok Park ,  Ilgeun Jung ,  Jinkuk Bae ,  Inyoung Lee ,  Sungdong Cho

IPC: H01L23/31 ,  H01L25/065 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L23/3171 ,  H01L23/3135 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L22/12 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/13016 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/14515 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/1436

Abstract: A semiconductor package may include a base, a first chip on the base, and first connection patterns that connect and couple the base and the first chip. The first chip may include a substrate, pad patterns on the substrate, a passivation layer on the substrate and having openings, and pillars on the substrate, the pad patterns include a first signal pad and a second signal pad, the first connection patterns are in contact with the pillars, the pillars include a first signal pillar in contact with the first signal pad and a second signal pillar in contact with the second signal pad, the openings in the passivation layer include a first opening having a sidewall facing a side surface of the first signal pillar and surrounding the side surface of the first signal pillar, and a second opening having a sidewall facing a side surface of the second signal pillar and surrounding the side surface of the second signal pillar, and a maximum width of the second opening is greater than a maximum width of the first opening.

公开(公告)号：US10937667B2

公开(公告)日：2021-03-02

申请号：US15930935

申请日：2020-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Lee ,  Hyunsoo Chung ,  Hansung Ryu ,  InYoung Lee

IPC: H01L21/50 ,  H01L23/48 ,  H01L23/00 ,  H01L23/58 ,  H01L23/373 ,  H01L21/48 ,  H01L21/02 ,  H01L23/544 ,  H01L25/065 ,  H01L21/768 ,  H01L23/31

Abstract: A semiconductor device including a substrate, an insulating layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

公开(公告)号：US20200343204A1

公开(公告)日：2020-10-29

申请号：US16923406

申请日：2020-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINCHAN AHN ,  Won-young Kim ,  Chanho Lee

IPC: H01L23/00 ,  H01L23/522

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a metal line layer on a semiconductor substrate, and a metal terminal on the metal line layer. The metal line layer includes metal lines, and a passivation layer having a non-planarized top surface including flat surfaces on the metal lines and a concave surface between the metal lines. The metal terminal is provided on the passivation layer. Opposite lateral surfaces of the metal terminal facing each other are provided on the flat surfaces of the passivation layer.

公开(公告)号：US09990986B1

公开(公告)日：2018-06-05

申请号：US15706859

申请日：2017-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ingyu Park ,  Inhak Lee ,  Chanho Lee ,  Jaeseung Choi

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  H01L27/11 ,  G11C5/06 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1096 ,  G11C11/412 ,  H01L27/1104

Abstract: A static random access memory device includes a plurality of memory cells arranged in rows and columns, a write driver configured to apply a bit line voltage corresponding to write data to a bit line extending in a column direction of the plurality of memory cells in a write operation, and a sub power line configured to transmit a cell driving voltage to the plurality of memory cells in the write operation and to extend in a direction parallel to the bit line, and includes a first node and a second node. The cell driving voltage is applied to the first node of the sub power line and the first node of the sub power line is aligned with an output node of the write driver in a row direction of the plurality of memory cells.

公开(公告)号：US11942143B2

公开(公告)日：2024-03-26

申请号：US17559110

申请日：2021-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Lee ,  Jung-Hak Song

IPC: G11C11/4097 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4087 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096

Abstract: A semiconductor memory device includes a memory cell array that includes memory cells arranged in rows and columns, a row decoder that is configured to receive a row address, decode the row address, and adjust voltages of selection lines based on the decoded row address, a word line driver that is connected with the selection lines, is connected with the rows of the memory cells through word lines, and is configured to adjust voltages of the word lines in response to an internal clock signal and the voltages of the selection lines, and a detection circuit that is connected with the word lines and is configured to activate a detection signal in response to voltages of the word lines being identical at a specific timing.

公开(公告)号：US20230352068A1

公开(公告)日：2023-11-02

申请号：US18124094

申请日：2023-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Duhwi Kim ,  Junghak Song ,  Chanho Lee

IPC: G11C7/10 ,  G11C8/08

CPC classification number: G11C7/1096 ,  G11C7/1087 ,  G11C7/1069 ,  G11C8/08

Abstract: A memory device includes a plurality of multi-bit cells, wherein each of the plurality of multi-bit cells includes a plurality of bit cells commonly connected to a column selection line, respectively connected to a plurality of write word lines, and respectively connected to a plurality of read word lines and an input circuit configured to provide a first signal corresponding to a bit to be written, to the plurality of bit cells, wherein each of the plurality of bit cells includes a latch circuit configured to receive the first signal in response to a write word line being activated and latch the first signal in response to the write word line being deactivated or a column selection line being deactivated, and a read circuit configured to output the first signal stored in the latch circuit to a bit line in response to a read word line being activated.