公开(公告)号：US20240371445A1

公开(公告)日：2024-11-07

申请号：US18402356

申请日：2024-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： TaeHyun Kim ,  HYUNJOONG KIM ,  Jichull JEONG ,  EUIHYUN CHEON

IPC: G11C16/26 ,  G11C5/06 ,  G11C16/04

Abstract: An operating method of a circuit design system which includes a processor and a memory includes reading, at the processor, a circuit layout of a flash memory device including a page buffer from the memory, initializing, at the processor, a value of a first parameter of at least one transistor of the page buffer and a value of a second parameter of at least one voltage applied to the page buffer, performing, at the processor, circuit simulation on the page buffer using the initialized first and second parameters, and calculating, at the processor, a reward based on a result of the circuit simulation. The processor is configured to perform, in response to the reward being not greater than a threshold value, a subsequent action. The subsequent action includes adjust the value of the first parameter of the at least one transistor and the value of the second parameter of the at least one voltage, and perform subsequent circuit simulation on the page buffer using the adjusted first and second parameters.

公开(公告)号：US20200312381A1

公开(公告)日：2020-10-01

申请号：US16590326

申请日：2019-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANG-WAN NAM ,  EUIHYUN CHEON ,  BYUNGJUN MIN

IPC: G11C5/06 ,  G11C16/16 ,  G11C16/08 ,  G11C16/30 ,  G11C7/18

Abstract: A nonvolatile memory device includes a first memory block including a plurality of cell transistors interconnected with a plurality of ground selection lines, a plurality of word lines, and a plurality of string selection lines, which are stacked in a direction perpendicular to a substrate, a block selecting circuit that is connected with the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines, and provides corresponding driving voltages to the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines in response to a block selection signal, respectively, and a block unselecting circuit that is connected only with specific string selection lines of the plurality of string selection lines, and provides an off-voltage only to the specific string selection lines in response to a block un-selection signal.

公开(公告)号：US20240126971A1

公开(公告)日：2024-04-18

申请号：US18124992

申请日：2023-03-22

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： HYUNJOONG KIM ,  TAEHYUN KIM ,  JICHULL JEONG ,  EUIHYUN CHEON

IPC: G06F30/392

CPC classification number: G06F30/392

Abstract: A layout optimization system for correcting a target layout of a semiconductor process includes a deep reinforcement learning (DRL) module, a memory storing instructions, and a processor configured to execute the instructions to receive a target layout, generate, by the DRL module, a prediction layout by applying a simulation to the target layout, generate, by the DRL module, an optimal layout based on the prediction layout, and apply a size correction to at least one pattern of the prediction layout based on the optimal layout.

公开(公告)号：US20200372956A1

公开(公告)日：2020-11-26

申请号：US16991912

申请日：2020-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANG-WAN NAM ,  EUIHYUN CHEON ,  BYUNGJUN MIN

IPC: G11C16/08 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C16/04 ,  G11C16/16

Abstract: A nonvolatile memory device includes a peripheral circuit region and a memory cell region. The peripheral circuit region includes a block selecting circuit, a block unselecting circuit, and a first metal pad. The memory cell region is vertically connected to the peripheral circuit region, and includes a first memory block and a second metal pad directly connected to the first metal pad. The block selecting circuit is connected with ground selection lines, word lines, and string selection lines, and provides corresponding driving voltages to the ground selection lines, the word lines, and the string selection lines in response to a block selection signal corresponding to the first memory block, respectively. The block unselecting circuit is connected only with specific string selection lines, and provides an off-voltage only to the specific string selection lines in response to a block un-selection signal.