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    NON-VOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME AND PROGRAM METHOD THEREOF
    1.
    发明申请
    NON-VOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME AND PROGRAM METHOD THEREOF 有权

    公开(公告)号：US20220068397A1

    公开(公告)日：2022-03-03

    申请号：US17523385

    申请日：2021-11-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： WON-TAECK JUNG ,  SANG-WAN NAM ,  JINWOO PARK ,  JAEYONG JEONG

    IPC: G11C16/20 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10

    Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.

    NONVOLATILE MEMORY DEVICE
    2.
    发明申请
    NONVOLATILE MEMORY DEVICE 审中-公开

    公开(公告)号：US20200312381A1

    公开(公告)日：2020-10-01

    申请号：US16590326

    申请日：2019-10-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SANG-WAN NAM ,  EUIHYUN CHEON ,  BYUNGJUN MIN

    IPC: G11C5/06 ,  G11C16/16 ,  G11C16/08 ,  G11C16/30 ,  G11C7/18

    Abstract: A nonvolatile memory device includes a first memory block including a plurality of cell transistors interconnected with a plurality of ground selection lines, a plurality of word lines, and a plurality of string selection lines, which are stacked in a direction perpendicular to a substrate, a block selecting circuit that is connected with the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines, and provides corresponding driving voltages to the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines in response to a block selection signal, respectively, and a block unselecting circuit that is connected only with specific string selection lines of the plurality of string selection lines, and provides an off-voltage only to the specific string selection lines in response to a block un-selection signal.

    OPERATING METHOD OF NONVOLATILE MEMORY AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    5.
    发明申请
    OPERATING METHOD OF NONVOLATILE MEMORY AND METHOD OF CONTROLLING NONVOLATILE MEMORY 审中-公开
    非易失性存储器的操作方法和控制非易失性存储器的方法

    公开(公告)号：US20150310923A1

    公开(公告)日：2015-10-29

    申请号：US14790572

    申请日：2015-07-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SANG-WAN NAM ,  KANG-BIN LEE ,  JUNGHOON PARK

    IPC: G11C16/26 ,  G11C16/12 ,  G11C16/04 ,  G11C16/34

    CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3459 ,  H01L27/1157 ,  H01L27/11582

    Abstract: An operating method of a nonvolatile memory, which includes a plurality of cell strings, each cell string having a plurality of memory cells and a string selection transistor stacked on a substrate, includes detecting threshold voltages of the string selection transistors of the plurality of cell strings; adjusting voltages to be supplied to the string selection transistors according to the detected threshold voltages; and applying the adjusted voltages to the string selection transistors to select or unselect the plurality of cell strings during a programming operation.

    Abstract translation: 一种非易失性存储器的操作方法，包括多个单元串，具有多个存储单元的每个单元串和堆叠在基板上的串选择晶体管，包括检测多个单元串中的串选择晶体管的阈值电压 ; 根据检测到的阈值电压调整提供给串选择晶体管的电压; 以及将调整后的电压施加到串选择晶体管，以在编程操作期间选择或取消选择多个单元串。

    NONVOLATILE MEMORY AND ERASING METHOD THEREOF
    6.
    发明申请
    NONVOLATILE MEMORY AND ERASING METHOD THEREOF 审中-公开
    非易失性存储器及其擦除方法

    公开(公告)号：US20150187425A1

    公开(公告)日：2015-07-02

    申请号：US14644247

    申请日：2015-03-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SANG-WAN NAM ,  WON-TAECK JUNG ,  JUNGHOON PARK

    IPC: G11C16/14 ,  G11C16/04

    CPC classification number: G11C16/14 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/344 ,  G11C16/3445 ,  H01L27/115

    Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.

    Abstract translation: 非易失性存储器的擦除方法包括向衬底提供擦除电压，将选择字线电压提供给与非易失性存储器的存储块内的选定子块相连的字线，将非选择字线电压提供给 在从提供擦除电压的时间点起的第一延迟时间期间，与存储器块内的未选择子块相连的字线，然后浮动与未选择的子块相连的字线。

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210005629A1

    公开(公告)日：2021-01-07

    申请号：US17025479

    申请日：2020-09-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： BONGSOON LIM ,  SANG-WAN NAM ,  SANG-WON PARK ,  SANG-WON SHIM ,  HONGSOO JEON ,  YONGHYUK CHOI

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11573 ,  H01L23/522 ,  G11C7/18 ,  H01L27/11519 ,  H01L27/11526 ,  G11C8/14

    Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.

    NONVOLATILE MEMORY DEVICE
    8.
    发明申请
    NONVOLATILE MEMORY DEVICE 审中-公开

    公开(公告)号：US20200372956A1

    公开(公告)日：2020-11-26

    申请号：US16991912

    申请日：2020-08-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SANG-WAN NAM ,  EUIHYUN CHEON ,  BYUNGJUN MIN

    IPC: G11C16/08 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C16/04 ,  G11C16/16

    Abstract: A nonvolatile memory device includes a peripheral circuit region and a memory cell region. The peripheral circuit region includes a block selecting circuit, a block unselecting circuit, and a first metal pad. The memory cell region is vertically connected to the peripheral circuit region, and includes a first memory block and a second metal pad directly connected to the first metal pad. The block selecting circuit is connected with ground selection lines, word lines, and string selection lines, and provides corresponding driving voltages to the ground selection lines, the word lines, and the string selection lines in response to a block selection signal corresponding to the first memory block, respectively. The block unselecting circuit is connected only with specific string selection lines, and provides an off-voltage only to the specific string selection lines in response to a block un-selection signal.

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