公开(公告)号：US20240242743A1

公开(公告)日：2024-07-18

申请号：US18368907

申请日：2023-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihyun Park ,  Jungyu Lee ,  Yumin Kim ,  Chiweon Yoon ,  Eunchan Lee

IPC: G11C7/04 ,  G11C7/08 ,  G11C7/10 ,  G11C7/14

CPC classification number: G11C7/04 ,  G11C7/08 ,  G11C7/1063 ,  G11C7/14

Abstract: A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a voltage generator configured to output a first voltage that varies according to temperature of the memory device, a second voltage that is constant regardless of the temperature, and a first reference voltage applied to at least one line among the plurality of word lines and the plurality of bit lines, and a temperature compensation circuit configured to generate a compensation offset voltage based on the first voltage and the second voltage, and output a second reference voltage based on the first reference voltage and the compensation offset voltage.

公开(公告)号：US20240233844A1

公开(公告)日：2024-07-11

申请号：US18471430

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunchan Lee ,  Jungyu Lee ,  Yumin Kim ,  Jihyun Park ,  Jayang Yoon

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

CPC classification number: G11C16/3495 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3459

Abstract: A device includes a first current mirror circuit including a plurality of first transistors, the plurality of first transistors including a common gate configured to receive a decoding signal according to a number of fail bits that are program-failed, a second current mirror circuit including a plurality of second transistors including a common gate configured to receive a reference current signal and a plurality of resistors respectively electrically connected to respective first terminals of the second transistors, and a comparison circuit configured to determine a compared result by comparing a first voltage corresponding to the decoding signal with respective ones of a plurality of second voltages output from the second current mirror circuit and configured to output a count signal corresponding to the compared result.