公开(公告)号：US11502097B2

公开(公告)日：2022-11-15

申请号：US16847210

申请日：2020-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunyeoung Choi ,  Suhyeong Lee ,  Yohan Lee ,  Yongseok Cho

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/423

Abstract: An integrated circuit device includes a channel layer in a channel hole penetrating a conductive line and an insulating layer, a charge trap pattern inside the channel hole between the conductive line and the channel layer, and a dummy charge trap pattern inside the channel hole between the insulating layer and the channel layer. In order to manufacture the integrated circuit device, a channel hole penetrating an insulating layer and a mold layer is formed. A mold indent connected to the channel hole is formed. A preliminary dielectric pattern is formed in the mold indent. The preliminary dielectric pattern is oxidized to form a first blocking dielectric pattern. A charge trap layer is formed in the channel hole. The mold layer is removed to form a conductive space. A portion of the charge trap layer is removed to form charge trap patterns and dummy charge trap patterns.

公开(公告)号：US20210066343A1

公开(公告)日：2021-03-04

申请号：US16847210

申请日：2020-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunyeoung Choi ,  Suhyeong Lee ,  Yohan Lee ,  Yongseok Cho

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/28 ,  H01L27/1157

Abstract: An integrated circuit device includes a channel layer in a channel hole penetrating a conductive line and an insulating layer, a charge trap pattern inside the channel hole between the conductive line and the channel layer, and a dummy charge trap pattern inside the channel hole between the insulating layer and the channel layer. In order to manufacture the integrated circuit device, a channel hole penetrating an insulating layer and a mold layer is formed. A mold indent connected to the channel hole is formed. A preliminary dielectric pattern is formed in the mold indent. The preliminary dielectric pattern is oxidized to form a first blocking dielectric pattern. A charge trap layer is formed in the channel hole. The mold layer is removed to form a conductive space. A portion of the charge trap layer is removed to form charge trap patterns and dummy charge trap patterns.

公开(公告)号：US10825833B1

公开(公告)日：2020-11-03

申请号：US16930711

申请日：2020-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunyeoung Choi ,  Hyung Joon Kim ,  Bio Kim ,  Yujin Kim ,  Junggeun Jee

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/532

Abstract: A semiconductor device includes a lower stack structure on a substrate, an upper stack structure on the lower stack structure, and a channel structure in a channel hole formed through the upper stack structure and the lower stack structure. The channel hole includes a lower channel hole in the lower stack structure, an upper channel hole in the upper stack structure, and a partial extension portion adjacent to an interface between the lower stack structure and the upper stack structure. The partial extension portion is in fluid communication with the lower channel hole and the upper channel hole. A lateral width of the partial extension portion may be greater than a lateral width of the upper channel hole adjacent to the partial extension portion and greater than a lateral width of the upper channel hole adjacent to the partial extension portion.

公开(公告)号：US10756107B2

公开(公告)日：2020-08-25

申请号：US16203790

申请日：2018-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunyeoung Choi ,  Hyung Joon Kim ,  Bio Kim ,  Yujin Kim ,  Junggeun Jee

IPC: H01L27/11582 ,  H01L23/532 ,  H01L27/1157

Abstract: A semiconductor device includes a lower stack structure on a substrate, an upper stack structure on the lower stack structure, and a channel structure in a channel hole formed through the upper stack structure and the lower stack structure. The channel hole includes a lower channel hole in the lower stack structure, an upper channel hole in the upper stack structure, and a partial extension portion adjacent to an interface between the lower stack structure and the upper stack structure. The partial extension portion is in fluid communication with the lower channel hole and the upper channel hole. A lateral width of the partial extension portion may be greater than a lateral width of the upper channel hole adjacent to the partial extension portion and greater than a lateral width of the upper channel hole adjacent to the partial extension portion.