公开(公告)号：US11502097B2

公开(公告)日：2022-11-15

申请号：US16847210

申请日：2020-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunyeoung Choi ,  Suhyeong Lee ,  Yohan Lee ,  Yongseok Cho

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/423

Abstract: An integrated circuit device includes a channel layer in a channel hole penetrating a conductive line and an insulating layer, a charge trap pattern inside the channel hole between the conductive line and the channel layer, and a dummy charge trap pattern inside the channel hole between the insulating layer and the channel layer. In order to manufacture the integrated circuit device, a channel hole penetrating an insulating layer and a mold layer is formed. A mold indent connected to the channel hole is formed. A preliminary dielectric pattern is formed in the mold indent. The preliminary dielectric pattern is oxidized to form a first blocking dielectric pattern. A charge trap layer is formed in the channel hole. The mold layer is removed to form a conductive space. A portion of the charge trap layer is removed to form charge trap patterns and dummy charge trap patterns.

公开(公告)号：US20210066343A1

公开(公告)日：2021-03-04

申请号：US16847210

申请日：2020-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunyeoung Choi ,  Suhyeong Lee ,  Yohan Lee ,  Yongseok Cho

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/28 ,  H01L27/1157

Abstract: An integrated circuit device includes a channel layer in a channel hole penetrating a conductive line and an insulating layer, a charge trap pattern inside the channel hole between the conductive line and the channel layer, and a dummy charge trap pattern inside the channel hole between the insulating layer and the channel layer. In order to manufacture the integrated circuit device, a channel hole penetrating an insulating layer and a mold layer is formed. A mold indent connected to the channel hole is formed. A preliminary dielectric pattern is formed in the mold indent. The preliminary dielectric pattern is oxidized to form a first blocking dielectric pattern. A charge trap layer is formed in the channel hole. The mold layer is removed to form a conductive space. A portion of the charge trap layer is removed to form charge trap patterns and dummy charge trap patterns.

公开(公告)号：US09601496B2

公开(公告)日：2017-03-21

申请号：US14109159

申请日：2013-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Lee ,  Hyunyong Go ,  Sunggil Kim ,  Kyong-Won An ,  Woosung Lee ,  Yongseok Cho

IPC: H01L29/78 ,  H01L27/108 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L27/10855 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of fabricating a semiconductor device, sacrificial layer patterns are formed by leaving portions of sacrificial layers, instead of completely removing the sacrificial layers. Thus, the reliability of the semiconductor device may be increased, and the process of manufacturing the same may be simplified.