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公开(公告)号:US20240021730A1
公开(公告)日:2024-01-18
申请号:US18475441
申请日:2023-09-27
Applicant: Samsung Electronics Co., Ltd.
Inventor: SOOJIN JEONG , DONG IL BAE , GEUMJONG BAE , SEUNGMIN SONG , JUNGGIL YANG
IPC: H01L29/78 , H01L29/06 , H01L29/423 , H01L27/092 , H01L29/08 , H01L29/786 , H01L29/66 , H01L21/8238 , H01L27/06
CPC classification number: H01L29/785 , H01L29/0653 , H01L29/42356 , H01L27/0924 , H01L29/0847 , H01L29/78654 , H01L29/42392 , H01L29/78618 , H01L29/66772 , H01L27/092 , H01L21/823807 , H01L27/0688 , H01L2029/7858
Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.
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公开(公告)号:US20200343378A1
公开(公告)日:2020-10-29
申请号:US16922464
申请日:2020-07-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: SOOJIN JEONG , DONG IL BAE , GEUMJONG BAE , SEUNGMIN SONG , JUNGGIL YANG
IPC: H01L29/78 , H01L29/06 , H01L29/423 , H01L27/092 , H01L29/08 , H01L29/786 , H01L29/66 , H01L21/8238 , H01L27/06
Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.
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公开(公告)号:US20190181257A1
公开(公告)日:2019-06-13
申请号:US16018121
申请日:2018-06-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: SOOJIN JEONG , DONG IL BAE , GEUMJONG BAE , SEUNGMIN SONG , JUNGGIL YANG
IPC: H01L29/78 , H01L29/06 , H01L29/08 , H01L29/423 , H01L27/092
Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.
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公开(公告)号:US20210202527A1
公开(公告)日:2021-07-01
申请号:US17199497
申请日:2021-03-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: HO-JUN KIM , JAEHYEOUNG MA , GEUMJONG BAE
IPC: H01L27/118 , H01L21/8238
Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include first and second active patterns on a substrate. Each of the first and second active patterns may extend in a first direction. The first and second active patterns may be aligned along the first direction and may be separated by a first trench extending in a second direction. The first trench may define a first sidewall of the first active pattern. The semiconductor devices may also include a channel pattern including first and second semiconductor patterns stacked on the first active pattern, a dummy gate electrode on the channel pattern and extending in the second direction, and a gate spacer on one side of the dummy gate electrode, the one side of the dummy gate electrode being adjacent to the first trench. The gate spacer may cover a first sidewall of the first active pattern.
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