公开(公告)号：US20190181257A1

公开(公告)日：2019-06-13

申请号：US16018121

申请日：2018-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOOJIN JEONG ,  DONG IL BAE ,  GEUMJONG BAE ,  SEUNGMIN SONG ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L27/092

Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.

公开(公告)号：US20220310651A1

公开(公告)日：2022-09-29

申请号：US17806842

申请日：2022-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGMIN SONG ,  KANGMIN KIM ,  JOONGSHIK SHIN ,  GEUNWON LIM

IPC: H01L27/11582

Abstract: A vertical memory device includes gate electrode structures, channels, first to third division patterns, and a first support layer. The gate electrode structure includes gate electrodes stacked in a first direction, and extends in a second direction. The gate electrode structures are spaced apart from one another in a third direction. The first division pattern extends in the second direction between the gate electrode structures. The second and third division patterns are alternately disposed in the second direction between the gate electrode structures. The first support layer is on the gate electrode structures at substantially the same height as upper portions of the first and second division patterns, and contacts the upper portions of the first and second division patterns. The upper portions of the first and second division patterns are arranged in a zigzag pattern in the second direction in a plan view.

公开(公告)号：US20230290881A1

公开(公告)日：2023-09-14

申请号：US18321962

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGMIN SONG ,  JUNBEOM PARK ,  BONGSEOK SUH ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/42392 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66545

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

公开(公告)号：US20220093786A1

公开(公告)日：2022-03-24

申请号：US17545072

申请日：2021-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGMIN SONG ,  JUNBEOM PARK ,  BONGSEOK SUH ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

公开(公告)号：US20240021730A1

公开(公告)日：2024-01-18

申请号：US18475441

申请日：2023-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOOJIN JEONG ,  DONG IL BAE ,  GEUMJONG BAE ,  SEUNGMIN SONG ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092 ,  H01L29/08 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/06

CPC classification number: H01L29/785 ,  H01L29/0653 ,  H01L29/42356 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/78654 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/66772 ,  H01L27/092 ,  H01L21/823807 ,  H01L27/0688 ,  H01L2029/7858

Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.

公开(公告)号：US20210134831A1

公开(公告)日：2021-05-06

申请号：US16902489

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGMIN SONG ,  KANGMIN KIM ,  JOONGSHIK SHIN ,  GEUNWON LIM

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A vertical memory device includes gate electrode structures, channels, first to third division patterns, and a first support layer. The gate electrode structure includes gate electrodes stacked in a first direction, and extends in a second direction. The gate electrode structures are spaced apart from one another in a third direction. The first division pattern extends in the second direction between the gate electrode structures. The second and third division patterns are alternately disposed in the second direction between the gate electrode structures. The first support layer is on the gate electrode structures at substantially the same height as upper portions of the first and second division patterns, and contacts the upper portions of the first and second division patterns. The upper portions of the first and second division patterns are arranged in a zigzag pattern in the second direction in a plan view.

公开(公告)号：US20190148403A1

公开(公告)日：2019-05-16

申请号：US16231710

申请日：2018-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGWON KIM ,  HYEONG PARK ,  HYUNMIN LEE ,  HOJONG KANG ,  JOOWON PARK ,  SEUNGMIN SONG

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.

公开(公告)号：US20240047339A1

公开(公告)日：2024-02-08

申请号：US18106540

申请日：2023-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGMIN CHA ,  SEUNGMIN SONG ,  YOUNGWOO KIM ,  JINKYU KIM ,  SORA YOU ,  NAMHYUN LEE ,  SUNGMOON LEE

IPC: H01L23/50 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L23/535 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/50 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/66545 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/4236 ,  H01L23/535 ,  H01L23/5226 ,  H01L23/5286

Abstract: An integrated circuit device includes a substrate, having a front surface and a rear surface opposite to each other, and a fin-type active region defined by a trench in the front surface, a device separation layer filling the trench, a source/drain region on the fin-type active region, a first conductive plug arranged on the source/drain region and electrically connected to the source/drain region, a power wiring line at least partially arranged on a lower surface of the substrate, a buried rail connected to the power wiring line through the device separation layer and decreasing in horizontal width toward the power wiring line, and a power via connecting the buried rail to the first conductive plug.

公开(公告)号：US20200381547A1

公开(公告)日：2020-12-03

申请号：US16743206

申请日：2020-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGMIN SONG ,  JUNBEOM PARK ,  BONGSEOK SUH ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423

Abstract: Integrated circuit devices including a fin shaped active region and methods of forming the same are provided. The devices may include a fin shaped active region, a plurality of semiconductor patterns on the fin shaped active region, a gate electrode on the plurality of semiconductor patterns, and source/drain regions on opposing sides of the gate electrode, respectively. The gate electrode may include a main gate portion extending on an uppermost semiconductor pattern and a sub-gate portion extending between two adjacent ones of the plurality of semiconductor patterns. The sub-gate portion may include a sub-gate center portion and sub-gate edge portions. In a horizontal cross-sectional view, a first width of the sub-gate center portion in a first direction may be less than a second width of one of the sub-gate edge portions in the first direction.

公开(公告)号：US20200343378A1

公开(公告)日：2020-10-29

申请号：US16922464

申请日：2020-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOOJIN JEONG ,  DONG IL BAE ,  GEUMJONG BAE ,  SEUNGMIN SONG ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092 ,  H01L29/08 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/06

Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.