公开(公告)号：US20210249413A1

公开(公告)日：2021-08-12

申请号：US17243943

申请日：2021-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHANG WOO NOH ,  MYUNG GIL KANG ,  GEUM JONG BAE ,  DONG IL BAE ,  JUNG GIL YANG ,  SANG HOON LEE

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/033 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/10

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.

公开(公告)号：US20180261668A1

公开(公告)日：2018-09-13

申请号：US15726535

申请日：2017-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG GIL YANG ,  SEUNG MIN SONG ,  SUNG MIN KIM ,  WOO SEOK PARK ,  GEUM JONG BAE ,  DONG IL BAE

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/78645

Abstract: A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.

公开(公告)号：US20240021730A1

公开(公告)日：2024-01-18

申请号：US18475441

申请日：2023-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOOJIN JEONG ,  DONG IL BAE ,  GEUMJONG BAE ,  SEUNGMIN SONG ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092 ,  H01L29/08 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/06

CPC classification number: H01L29/785 ,  H01L29/0653 ,  H01L29/42356 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/78654 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/66772 ,  H01L27/092 ,  H01L21/823807 ,  H01L27/0688 ,  H01L2029/7858

Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.

公开(公告)号：US20180218950A1

公开(公告)日：2018-08-02

申请号：US15937037

申请日：2018-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MICRO CANTORO ,  MARIA TOLEDANO LUQUE ,  YEONCHEOL HEO ,  DONG IL BAE

IPC: H01L21/8238 ,  H01L21/02

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.

公开(公告)号：US20240234343A1

公开(公告)日：2024-07-11

申请号：US18612304

申请日：2024-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： NOH YEONG PARK ,  BEOMJIN PARK ,  DONG IL BAE ,  Sangwon BAEK ,  HYUN-SEUNG SONG

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L23/562 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate including a first region and a second region and a first active pattern on the first region. The first active pattern may include a pair of first source/drain patterns and a first channel pattern therebetween, and the first channel pattern may include a plurality of first semiconductor patterns stacked on the substrate. The semiconductor device may further include a first gate electrode, which is provided on the first channel patterns, and a supporting pattern, which is provided on side surfaces of the plurality of first semiconductor patterns to connect the side surfaces of the plurality of first semiconductor patterns to each other.

公开(公告)号：US20190181257A1

公开(公告)日：2019-06-13

申请号：US16018121

申请日：2018-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOOJIN JEONG ,  DONG IL BAE ,  GEUMJONG BAE ,  SEUNGMIN SONG ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L27/092

Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.

公开(公告)号：US20220173053A1

公开(公告)日：2022-06-02

申请号：US17352503

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： NOH YEONG PARK ,  BEOMJIN PARK ,  DONG IL BAE ,  Sangwon BAEK ,  HYUN-SEUNG SONG

IPC: H01L23/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device may include a substrate including a first region and a second region and a first active pattern on the first region. The first active pattern may include a pair of first source/drain patterns and a first channel pattern therebetween, and the first channel pattern may include a plurality of first semiconductor patterns stacked on the substrate. The semiconductor device may further include a first gate electrode, which is provided on the first channel patterns, and a supporting pattern, which is provided on side surfaces of the plurality of first semiconductor patterns to connect the side surfaces of the plurality of first semiconductor patterns to each other.

公开(公告)号：US20200343378A1

公开(公告)日：2020-10-29

申请号：US16922464

申请日：2020-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOOJIN JEONG ,  DONG IL BAE ,  GEUMJONG BAE ,  SEUNGMIN SONG ,  JUNGGIL YANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092 ,  H01L29/08 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/06

Abstract: A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.

公开(公告)号：US20190371680A1

公开(公告)日：2019-12-05

申请号：US16541416

申请日：2019-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MIRCO CANTORO ,  MARIA TOLEDANO LUQUE ,  YEONCHEOL HEO ,  DONG IL BAE

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.

公开(公告)号：US20190165157A1

公开(公告)日：2019-05-30

申请号：US16011785

申请日：2018-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggil Yang ,  Seungmin Song ,  Geumjong Bae ,  DONG IL BAE

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.